An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversion in mixed-signal systems, such as neuromorphic chips and neural networks. D/A conversion is integrated into the SRAM readout by charge sharing of the proposed split bit-line (BL). Also, A/D conversion is integrated into the SRAM write operation with the successive approximation method in the proposed inout (IO) block. Also, a configurable SRAM bit-cell array is proposed to allocate the converted digital data without unfilled bit-cells. The multi-row access decoder selects multiple bit-cells in a single column and configures the bit-cell array by controlling the BL switches to split BLs. The proposed A-SRAM is implemented using 65 nm CMOS technology. It achieves 17.5 fJ/bit energy-efficiency and 21 Gbit/s throughput for the analog readout, which are 64% and 1.3× better than those of the conventional SRAM followed by a DAC. Also, the area is reduced by 91% compared to the conventional SRAM with ADC and DAC.