Fast timing simulation of custom digital circuits through HDL modeling = 하드웨어 기술 언어 모델링을 통한 커스텀 디지털 회로의 고속 타이밍 시뮬레이션

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We suggest methodology to estimate timing of custom digital design without slow SPICE simulation and logic verification methodology. Delay of logic gates that consists of transistors is different according to input vectors. We suggest method to estimate delay considering input vectors. To improve the accuracy of the propagation delay, we considered Miller capacitance. We applied the effective turn-on resistance of transistors which could be different due to the position of transistors. Also, we proposed the method can reduce the error of slew calculation compared to conventional slew calculation method, and we adjusted cell delay according to calculated slew. Due to the wire, delay can be added. We estimate the wirelength using the coordinate of cells and applied the propagation delay due to wire. Experimental result shows that the proposed timing simulation flow accelerated runtime about 500 times compared to SPICE simulation. Also, accuracy enhancement techniques reduced the error of delay estimation by 15\% averagely
Advisors
Shin, Youngsooresearcher신영수researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[iv, 35 p. :]

Keywords

Custom digital circuit; Timing; Propagation delay; Slew; Runtime; 커스텀 디지털 회로; 타이밍; 지연 시간; 천이 시간; 실행 속도

URI
http://hdl.handle.net/10203/243307
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675415&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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