Through-silicon via (TSV) technology has emerged as a key component of 3-D integrated circuits. As the integration density in a package increases, the nonlinear metal-oxide-semiconductor (MOS) capacitance in TSVs has a greater effect on the electrical performance of the devices. Imperfections due to the deposition of a dielectric layer are important factors which can change the characteristics of the MOS capacitance. This letter presents a method by which to detect the interface-trap charge density D-it and lateral nonuniformity (LNU) of imperfections in TSVs. The results of an analysis of a measured sample define Dit and LNU at the dielectric-semiconductor interface and demonstrate that the presence of LNU can be established by a negative D-it.