Highly purified carbon nanotube transistor and circuit applications

Abstract

Recently, various novel functional materials, and scaled device fabrication techniques have emerged in the field of nano-electronics. Semiconducting single-walled carbon nanotubes (SWNTs) are considered to be some of the most promising semiconductors for FETs due to their advantages such as high electrical performance, yielding scalable, air-stability, and flexibility. In this dissertation, SWNTs are employed as p-channel semiconductors in FETs, integrated into structural engineering using CMOS process and flexible all p-type circuits through use of the cost-effective inkjet printing technique. Throughout the four parts of this paper, fabrication, engineering and analysis of carbon nanotube field-effect transistors (CNT-FETs) are discussed regarding purity, density and device structures. In the first part, it is experimentally demonstrated high-yield, high-performance TFTs composed of a highly purified single-walled carbon nanotube (SWNT) network. A solution process for a highly separated 99.9% semiconducting SWNT solution is used to acquire a significant enhancement in transistor performance, such as a high on/off ratio, high mobility, and high yields close to 100%. In the second part, the three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated. In particular, the 3-D CNT-FETs are feasible for wafer-scale process-based circuit, improves the gate controllability thanks to the 3-D geometric advantage thereby resulting in the suppression of the short-channel effects (SCEs) such as the subthreshold swing (SS) and corresponding off-state leakage current. In the third part, fully wrap-gated carbon nanotube (CNT) transistors with vertically suspended (VS) semiconducting single-walled CNTs, purified up to 99.9%, are demonstrated for the first time. Without a sacrifice of scalability, remarkably enhanced gate controllability and charge transport capabilities were achieved due to the geometrical advantage of the gate-all-around (GAA) structure with multiple channels. The VS channels were formed with the aid of a silicon-processed vertically integrated nanowire frame, offering high completeness and compatibility with silicon processes. This approach will increase the applicability of CNTs toward high-performance emerging materials. In the fourth part, logic circuits composed of top-gate carbon nanotube thin-film transistors (CNT-TFTs) on a flexible polymeric (polyethersulfone, PES) substrate was demonstrated. Highly purified semiconducting CNTs (99.9%) are used for a channel in TFTs with an ultrathin poly (1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) polymer gate dielectric, which was deposited by ‘initiated chemical vapor deposition (iCVD)’. Pattern delineation for electrodes was completed by use of ink-jet printing. The purified CNTs with high quality of the pV3D3 gate dielectric boost electrical performances. Thus, this research suggests potential for use in the production of low-cost and large-scale futuristic soft electronics.