A robust 400 MHz super-regenerative receiver with low susceptibility to clock jitter is proposed. The conventional un-clocked envelope detector (ED) is replaced with a synchronous peak-held ED, where its peak detection value is kept during oscillator quenching OFF time by switching off the charging path of ED, synchronously with quenching clock. In this way, the flattened peak level not only allows the use of low quality jitter in the clock but also removes a tedious timing calibration process in the conventional receiver. The proposed receiver with the novel synchronous peak-held ED and an on-chip oscillator achieves a sensitivity performance of -81 dBm@1 Mbps without the conventional ADC sampling timing calibration. The receiver in 180 nm CMOS occupies an active area of 0.51 mm(2) and dissipates 570 mu W.