ENCODING, DECODING, AND MULTI-STAGE DECODING CIRCUITS FOR CONCATENATED BCH, AND ERROR CORRECTION CIRCUIT OF FLASH MEMORY DEVICE USING THE SAME

Abstract

The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof.