Low-power and all-digital phase interpolator-based clock and data recovery architecture

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The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.
Assignee
KAIST
Country
US (United States)
Issue Date
2015-10-20
Application Date
2013-03-18
Application Number
13846688
Registration Date
2015-10-20
Registration Number
9166605
URI
http://hdl.handle.net/10203/232011
Appears in Collection
EE-Patent(특허)
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