Wigner transport simulation of (core gate) silicon-shell nanowire transistors in cylindrical coordinates

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dc.contributor.authorLee, Joon-Hoko
dc.contributor.authorJeong, Woo Jinko
dc.contributor.authorSeo, Junbeomko
dc.contributor.authorShin, Mincheolko
dc.date.accessioned2017-12-19T00:57:10Z-
dc.date.available2017-12-19T00:57:10Z-
dc.date.created2017-11-29-
dc.date.created2017-11-29-
dc.date.issued2018-01-
dc.identifier.citationSOLID-STATE ELECTRONICS, v.139, pp.101 - 108-
dc.identifier.issn0038-1101-
dc.identifier.urihttp://hdl.handle.net/10203/228424-
dc.description.abstractGate-all-around silicon nanowire transistors (SNWTs) are recognized as promising candidates to reduce problems due to quantum effects in conventional nano-transistors. In this study we investigate whether structural modification of SNWTs leads to improved performance. A model calculation for a transistor with a channel length of several nanometers requires a quantum transport simulator, and we use a Wigner transport equation (WTE) discretized by a third-order upwind differential scheme (TDS) suggested by Yamada et al. (2009) for quantum transport simulations of gate-all-around silicon-shell nanowire transistors (SSNWTs), core gate SSNWTs (CG-SSNWTs), and independent CG-SSNWTs (ICG-SSNWTs). A WTE discretized by the TDS is known to produce highly accurate results. The SSNWT has a structure in which an insulator cylinder is inserted into the center axis of the SNWT, and the CG-SSNWT has a structure in which a core gate is inserted into the center axis of the SSNWT. The calculations show that the performances of the SSNWTs are improved by introducing the Si-shell structure and the core gate. The ICG-SSNWTs are identical in structure to the CG-SSNWTs, but the outer and core gates are independently biased. The calculations for the ICG-SSNWTs show that the threshold voltage can be controlled using the difference between the core and outer gate voltages.-
dc.languageEnglish-
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD-
dc.subjectSCHOTTKY-BARRIER MOSFETS-
dc.subjectELECTRON-TRANSPORT-
dc.subjectQUANTUM-TRANSPORT-
dc.subjectDEVICES-
dc.subjectPERFORMANCE-
dc.subjectFINFETS-
dc.titleWigner transport simulation of (core gate) silicon-shell nanowire transistors in cylindrical coordinates-
dc.typeArticle-
dc.identifier.wosid000417283000015-
dc.identifier.scopusid2-s2.0-85032797863-
dc.type.rimsART-
dc.citation.volume139-
dc.citation.beginningpage101-
dc.citation.endingpage108-
dc.citation.publicationnameSOLID-STATE ELECTRONICS-
dc.identifier.doi10.1016/j.sse.2017.10.041-
dc.contributor.localauthorShin, Mincheol-
dc.contributor.nonIdAuthorLee, Joon-Ho-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordPlusSCHOTTKY-BARRIER MOSFETS-
dc.subject.keywordPlusELECTRON-TRANSPORT-
dc.subject.keywordPlusQUANTUM-TRANSPORT-
dc.subject.keywordPlusDEVICES-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusFINFETS-
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