DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seol, Hoseok | ko |
dc.contributor.author | Shin, Wongyu | ko |
dc.contributor.author | Jang, Jaemin | ko |
dc.contributor.author | Choi, Jungwhan | ko |
dc.contributor.author | Suh, Jinwoong | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2017-11-20T08:24:57Z | - |
dc.date.available | 2017-11-20T08:24:57Z | - |
dc.date.created | 2017-11-14 | - |
dc.date.created | 2017-11-14 | - |
dc.date.issued | 2017-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.11, pp.3251 - 3254 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/227047 | - |
dc.description.abstract | Initializing memory with zero data is essential for safe memory management. However, initializing a large memory area slows down the system significantly. The most likely cause for initialization to slow down the system is the limited DRAM initialization method. At present, the only way to initialize DRAM area is to execute multiple WRITE commands. However, the WRITE command slows the initialization because of its small granularity and data bus occupancy. In this brief, we propose an efficient in-DRAM initialization method inspired by the internal structure and operation of DRAM. The proposed method, called row reset, uses a DRAM row buffer to zero out a single DRAM row at a time. Row Reset allows for parallel initialization on multiple DRAM banks without using off-chip data transfer, thus reducing initialization time by up to 63 times. Row reset is a practical approach, because it can be implemented with existing circuitry in DRAM without additional area overhead. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | In-DRAM Data Initialization | - |
dc.type | Article | - |
dc.identifier.wosid | 000413754400024 | - |
dc.identifier.scopusid | 2-s2.0-85028502218 | - |
dc.type.rims | ART | - |
dc.citation.volume | 25 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 3251 | - |
dc.citation.endingpage | 3254 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2017.2737646 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Seol, Hoseok | - |
dc.contributor.nonIdAuthor | Suh, Jinwoong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bulk zeroing | - |
dc.subject.keywordAuthor | DRAM initialization | - |
dc.subject.keywordAuthor | in-memory processing | - |
dc.subject.keywordAuthor | page initialization | - |
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