A 2.3-mW 0.01-mm(2) 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS

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In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop filter so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed, which allows the use of a simple 1-bit TDC instead of a power-hungry wide-dynamic range TDC. Implemented in 65-nm CMOS, the prototype chip achieves less than 1.1-ps phase error for a 1.25-GHz quadrature signal and occupies an active area of only 0.01 mm(2) while consuming 2.27 mW from a 1.0-V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-04
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.4, pp.397 - 401

ISSN
1549-7747
DOI
10.1109/TCSII.2016.2569441
URI
http://hdl.handle.net/10203/223921
Appears in Collection
EE-Journal Papers(저널논문)
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