Hardware optimizations for advanced forward error correction

Abstract

Forward error-correction (FEC) codes have been widely applied to recover erroneous information without retransmitting the codeword. Due to the data integrity, the decoder of error-correction codes (ECCs) has been an essential hardware in various mobile applications such as wireless, optical and storage systems. Recently, more advanced coding systems having stronger error-correction capabilities are necessary to over-come the severe channel conditions. The decoding complexity, unfortunately, increases exponentially to sup-port such a strong error-correction. Moreover, the high-throughput decoder architecture gratifying the recent high-speed host interfaces necessitates massive-parallel operations, requiring the impractical hardware com-plexity and power consumption. To enhance the overall system performance, it is requested to develop novel optimization techniques that relax the hardware costs of the advanced ECC decoders. In this dissertation, the hardware optimizations are studied to relax the decoding power and com-plexity in various ECCs. We consider BCH and LDPC codes and their extensions, which are actively applied to the communication systems. To reduce the hardware complexity of each coding system, the common hardware resources are gathered to eliminate redundant units as many as possible. The dedicated folding technique is proposed to reuse the processing elements without sacrificing the decoding throughput. In addition, the size of buffers that store the intermediate data is minimized by generating essential values without accessing the original codeword. For the energy-efficient decoding architecture, the number of on-chip memory accesses is minimized. Based on the channel condition, moreover, some processing resources are disabled to reduce the dynamic power when the channel is clean enough to correct all the error bits with the simplified computations. For the fair comparison, the proposed optimization schemes are realized while targeting the same ap-plication, i.e., the storage system associated with MLC NAND flash memories. Moreover, the whole SoC platform including microprocessor, on-chip high-speed bus, programmable DMA, multi-threaded flash memory controller, high-speed external memory and interface controllers is designed to collaborate with the proposed ECC decoder. Based on the SoC platform, multiple prototypes are fabricated and verified in recent CMOS processes. As a result, the proposed algorithms contribute on the high performance coding system which is vastly superior to the state-of-the-arts in terms of error-correcting capability, decoding throughput, hardware complexity and energy-efficiency.