Area-efficient low-power VLSI architectures for modern linear block codes

Abstract

Recently the error-correcting codes have become one integral part in nearly all the modern communication and storage systems as the retransmissions are costly or sometimes impossible. After Claude Shannon defined the theoretical maximum information rate given a particular channel, numerous error-correcting codes have developed to approach the channel capacity. Among various error-correction codes used to recover corrupted codewords, this dissertation is devoted to developing efficient VLSI architectures for modern linear block codes, especially focusing on the widely-used BCH code and the newly-discovered polar code. Due to its superior error-correction performance and affordable hardware complexity, the Bose-Chaudhuri-Hocquenghem (BCH) code is one of the most widely used linear algebraic codes. The binary BCH code has been employed in diverse systems such as advanced solid-state storages and digital video broadcasting systems, as it can guarantee multiple erroneous-bit corrections. Most of the applications are continuously demanding ever higher decoding throughput as well as ever larger error-correction capability, and these requirements makes small-area and low-power structures become more important in BCH hardware. This dissertation proposes on-demand syndrome scheduling and common-sub expression sharing technique to alleviate the hardware complexity, and two-step approach to relax the power consumption. Moreover, architectural optimization to support multiple codes with a single hardware is developed. Using the mathematical properties, the proposed multimode structure selectively activates only a necessary part of the configurable error-correction circuitry. Furthermore, the polar code is a new class of error-correcting codes that provably achieves the capacity of the underlying channels. Various theoretic aspects of the polar code including code construction and decoding algorithms have been investigated in the previous works, but VLSI hardware architectures for the polar code have rarely been discussed. As the polar code achieves the channel-achieving property asymptotically, it should be long enough to have a good error-correcting performance. Moreover, due to the inherent serial nature of the successive-cancellation (SC) decoding algorithm, the SC decoders suffer from a long latency leading to a poor throughput. This dissertation presents a new partially parallel encoder architecture effective in alleviating the hardware complexity and a syndrome-check decoding algorithm that can directly decode information bits without recursive computations. The prototype designs based on the proposed algorithms are simulated and verified in 130 nm CMOS process. The experimental results show that the proposed optimizations contribute on the area-efficient low-power VLSI implementation which is highly superior to the state-of-the-arts in terms of hardware complexity, decoding throughput, and energy-efficiency.