As communication technology and scaling technology are developed, techniques for high data rate and low power consumption have researched in chip-to-chip parallel interfaces. Transceivers which are de-veloped by these techniques have focused on achieving low energy efficiency. It has been achieved by ad-vanced clocking in I/O circuits. According to clocking method, there are two of the most important classes: embedded clock (EC) architecture and forwarded clock (FC) architecture. Comparing to the EC architecture which transmits only data through channel, the FC architecture which is also called as a source synchronous parallel link (SSPL) has an additional clock channel to transmit clock as well as data. The FC architecture is well suited for low power consumption and a high aggregate bandwidth trend due to a simple clock recovery circuit and inherently high jitter correlation between data and clock. Due to these advantages, many recent technologies such as DRAM Interface, QuickPath Interconnect (QPI), and Hyper-Transport adopt the SSPL. Nevertheless, there are various issues, such as skew compensation, maintaining high jitter correlation between data and clock, and multiphase clock generation to improve the data rate in the FC architecture.
To address these issues, many researches have been investigated for clock recovery circuits in the FC receiver. Recently, many papers have focused on injection-locked oscillators (ILOs) because ILOs can easily perform clock de-skew, and they can provide a controllable and wide jitter tracking bandwidth (JTB), which could be optimal for the FC architecture in terms of jitter correlation between data and clock. Despite these advantages, it is hard to adopt simple ILOs in practical systems due to several issues. First, there is intrinsic dependency between the JTB and de-skew. If the difference between the free running frequency and injec-tion clock frequency increases for large de-skewing, the JTB is seriously reduced. Second, there is a depend-ency between the VCO tuning range and the JTB of the ILO. In addition, when one-point injection scheme is used, it is hard to generate accurate multiphase clock for exploiting interleaving scheme. Above these issues, the receiver using ILO for clock jitter filter is sensitive to power noise as the latency mismatch between data and clock increases. Moreover, as latency mismatch increases, jitter correlation between data and sampling clock is reduced because high frequency jitter at ILO is note removed but replaced by the uncorrelated phase noise of oscillator. This dissertation proposes two receivers with novel schemes to increase jitter correlation.
At first, a quarter-rate FC receiver based on the ILO which exploits a phase shifting phenomenon is proposed to minimize the effect of the dependency between the JTB and de-skew. In the phase shifting phe-nomenon, phases of the output clock are shifted by the duty-cycle of an injection clock. To utilize this phase shifting phenomenon, we proposed a quarter-rate receiver which includes a simple duty-cycle adjuster (DCA). By using the DCA, the proposed receiver can simultaneously achieve low JTB variation, a wide JTB, and a high data rate while maintaining low power consumption. The proposed receiver achieves a 12 Gb/s data rate with 0.92 mW/Gb/s in a 1 V 65 nm CMOS process.
A second novel receiver which is robust against power noise and has high jitter correlation with high frequency jitter is proposed. The forwarded-clock receiver using a proposed mixing cell integrated injection-locked oscillator (MIILO) and an I/Q generator based on injection-locked oscillator (IQGILO). By using MIILO, jitter tolerance is enhanced by about 1.8 times at high frequency compared to using a conventional injection-locked oscillator. In addition, the proposed receiver is robust against power supply induced jitter (PSIJ) caused by a clock distribution network because jitter tracking bandwidth of IQGILO is always lower than peak frequency of PSIJ regardless of latency mismatch between data and clock. The test chip achieves 9.6 Gb/s data rate with 0.96 mW/Gb/s and occupies only 0.0162 mm2 in a 1 V 65 nm CMOS.