Eletrothermal analysis of poly-si nanowire and its application to localized annealing of gate-all-around field-effect transistor

Abstract

The importance of poly-crystalline silicon (poly-Si) in semiconductor manufacturing is rapidly increas-ing due to its highly controllable conductivity and excellent, uniform deposition quality. With the continuing miniaturization of electronic components, low dimensional structures such as 1-dimensional nanowires (NWs) have attracted a great deal of attention. But such components have a much higher current density than 2- or 3- dimensional films, and high current can degrade device lifetime and lead to breakdown problems due to the high temperature. First, we report on the electrical and thermal characteristics of poly-Si NWs, which can also be used to control electrical and physical breakdown under high current density. This work reports a con-trollable catastrophic change of poly-Si NWs by thermally-assisted electromigration and underlying mecha-nisms. It also reports the direct and real time observation of these catastrophic changes of poly-Si nanowires for the first time, using scanning electron microscopy. However, aforementioned thermal characteristics including catastrophic breakdown of the poly-Si nanowires are not always regarded as detrimental problems in nanotechnology. If the current density and corresponded thermal properties can be controlled properly, poly-Si NW can be used advantageously. For example, the NW can be utilized as a built-in heater in MOSFET. The heater generated Joule heat, and re-paired the degradation induced by hot-carrier injection successfully. The concentrated high temperature an-neals the gate oxide locally and degraded device parameters are recovered or further enhanced within a short time of 1 ms. Selecting a proper range of repair voltage is very important to maximize the annealing effects and minimize extra damages caused by excessive high temperature. The repairing voltage is related to the resistance of the poly-Si gate according to the device scaling.