(A) scale-space processor with two-dimensional cache for real-time object recognition

Abstract

A scale-space processor with two-dimensional cache is proposed to achieve real-time object recogni-tion in HD 720p images. Scale-space is the most common concept to achieve scale-invariant property in ob-ject recognition, however its high computation cost and frequent memory access makes it hard to implement a real-time object recognition processor. We employ hierarchical convolution accelerator (HCA) which com-putes multiple convolutions in a single cycle with various kernel sizes. In addition, two-dimensional cache (2D Cache) supports accessing column-wise consecutive data from any image window with reduced area. A pre-fetch controller for the proposed 2D Cache improves the hit rate by exploiting the sequential access pattern of convolution tasks. As a result, the scale-space processor implemented in a 65nm CMOS technology achieves 42.7fps on a HD 720p image and consumes 25.1mW for 30fps real-time operation. It shows 3.22x throughput im-provement, 4.44x power reduction, and 6.25x area reduction compared to the previous state-of-the-arts ob-ject recognition system-on-chips.