Design and analysis of high bandwidth memory (HBM) interposer considering signal and power integrity (SI/PI) for terabyte/s bandwidth system

Abstract

As total system bandwidth increased, a semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. To establish HBM based interface, it becomes essential to fabricate Silicon interposer due to its capability to process narrow signal width and space. Therefore, Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. Since the channels performance is dominantly determined by HBM interposer, the design and analysis of signal and power integrity (SI/PI) for HBM interposer must be preceded thoroughly to guarantee the entire system performance. For the signal integrity, design optimization of HBM interposer channels considering routing feasibility is discussed. In order to analyze channel characteristics to determine an optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM interposer are analyzed with the comparison of eye-opening voltage and timing jitter using 3D electromagnetic (EM) solver and SPICE. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity. For PDN impedance analysis, Z-parameters depending on the various physical dimensions considering proposed PDN structures are simulated and compared. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully show that HBM interposer PDN can play an important role for the suppression of SSN.