(A) Low Latency DRAM Architecture Exploiting Row Duplication

Abstract

As DRAM performance becomes important in computer performance, it is important to improve DRAM bandwidth and DRAM latency. DRAM latency can be improved by modifying DRAM bank structure. However, modification of the bank structure can incur large area-overhead. To reduce DRAM latency without bank modification, we propose a low latency DRAM architecture which is called Multiple Clone Row DRAM (MCR-DRAM). We use two key observations to reduce DRAM latency. First observation is that sensing process of a high capacitance cell is faster. Second observation is that short DRAM cell refresh interval enables the cell to have the lower maximum charge leakage. The first observation makes it possible to early issue a READ or WRITE command by making sensing process fast (Early-Access). From the second observation, a PRECHARGE command can be early issued in spite of not fully restored cells (Early-Precharge) and refresh time reduction is available by not fully refreshing the cells (Fast-Refresh). However, the observations have disadvantages which are large DRAM cell size and additional REFRESH commands. The mechanisms (Early-Access, Early-Precharge and Fast-Refresh) are applied to Multiple Clone Row (MCR). An MCR is a set of multiple rows which become a logically single row by simultaneously turning on or off the multiple rows. This activity to make MCR is called row duplication. The disadvantages due to the observations can be solved by concurrently sensed-cells and a shorter cell refresh interval of an MCR. To implement the MCR with low area-overhead, we add our MCR generator not to a DRAM bank but to a peripheral region. MCR-DRAM can be dynamically changed from low capacity and latency DRAM to existing capacity and latency DRAM. Our simulation results show that, on average, execution time/read latency/EDP of single-core and multi-core simulations in mode [4/4x/100%reg] are reduced by 8.3%/13.1%/14.1% and 11.2%/11.4%/23.2%, respectively.