DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Taigon | ko |
dc.contributor.author | Panth, Shreepad | ko |
dc.contributor.author | Chae, Yoo-Jin | ko |
dc.contributor.author | Lim, Sung Kyu | ko |
dc.date.accessioned | 2017-01-18T02:37:08Z | - |
dc.date.available | 2017-01-18T02:37:08Z | - |
dc.date.created | 2017-01-02 | - |
dc.date.created | 2017-01-02 | - |
dc.date.issued | 2016-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.35, no.12, pp.2056 - 2067 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | http://hdl.handle.net/10203/219614 | - |
dc.description.abstract | Low-power is one of the key driving forces in modern very large scale integration systems. Recent studies show that 3-D integrated circuits (ICs) offer a significant power saving over 2-D ICs. However, these studies are mainly limited to two-tier (2-tier) designs. Thus, in this paper, we extend our target to three-tier (3-tier) 3-D ICs. This paper first shows that the one additional tier available in 3-tier 3-D ICs does offer more power saving compared with their 2-tier 3-D IC counterparts, but more careful floorplanning, through-silicon via management, and block folding considerations are required. Second, we find that the 3-tiers can be bonded in several different ways: 1) face-to-back only; 2) face-to-face and face-to-back combined; and 3) back-to-back and face-to-face combined. This paper shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective computer-aided-design solutions that are seamlessly integrated into commercial 2-D IC tools to handle 3-tier 3-D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3-D ICs provide -14.8% more power reduction over 2-tier 3-D ICs, and -36.0% over 2-D ICs in microprocessor cores under the same performance. In full-chip microprocessors, our 3-tier 3-D ICs provide -27.2% more power reduction over 2-D ICs. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs | - |
dc.type | Article | - |
dc.identifier.wosid | 000388960900011 | - |
dc.identifier.scopusid | 2-s2.0-84999115008 | - |
dc.type.rims | ART | - |
dc.citation.volume | 35 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 2056 | - |
dc.citation.endingpage | 2067 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.identifier.doi | 10.1109/TCAD.2016.2550583 | - |
dc.contributor.localauthor | Chae, Yoo-Jin | - |
dc.contributor.nonIdAuthor | Song, Taigon | - |
dc.contributor.nonIdAuthor | Panth, Shreepad | - |
dc.contributor.nonIdAuthor | Lim, Sung Kyu | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | 3D IC | - |
dc.subject.keywordAuthor | floorplanning | - |
dc.subject.keywordAuthor | TSV | - |
dc.subject.keywordAuthor | F2F (face-to-face) | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | power reduction | - |
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