A 19-mW 2.6-mm(2) L1/L2 dual-band CMOS GPS receiver

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This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for dual-band operation. The receiver is composed of an RF pream-plifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked-loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-mu m CMOS technology, the receiver exhibits maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying a 2.6-mm(2) die area including the ESD I/O pads.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2005-07
Language
English
Article Type
Article; Proceedings Paper
Keywords

LOW-POWER; 0.18-MU-M CMOS; RADIO; FILTER; CHIP

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, pp.1414 - 1425

ISSN
0018-9200
URI
http://hdl.handle.net/10203/21468
Appears in Collection
EE-Journal Papers(저널논문)
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