Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

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dc.contributor.authorWang, Boko
dc.contributor.authorTruc Quynh Nguyenko
dc.contributor.authorDo, Anh Tuanko
dc.contributor.authorZhou, Junko
dc.contributor.authorJe, Minkyuko
dc.contributor.authorKim, Tony Tae-Hyoungko
dc.date.accessioned2016-12-01T07:02:41Z-
dc.date.available2016-12-01T07:02:41Z-
dc.date.created2016-11-21-
dc.date.created2016-11-21-
dc.date.created2016-11-21-
dc.date.created2016-11-21-
dc.date.created2016-11-21-
dc.date.issued2015-02-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.2, pp.441 - 448-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10203/214567-
dc.description.abstractThis paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 mu s. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V similar to 0.6 V by the proposed CAM-assisted circuit.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleDesign of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement-
dc.typeArticle-
dc.identifier.wosid000349399800012-
dc.identifier.scopusid2-s2.0-85027940188-
dc.type.rimsART-
dc.citation.volume62-
dc.citation.issue2-
dc.citation.beginningpage441-
dc.citation.endingpage448-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.identifier.doi10.1109/TCSI.2014.2360760-
dc.contributor.localauthorJe, Minkyu-
dc.contributor.nonIdAuthorWang, Bo-
dc.contributor.nonIdAuthorTruc Quynh Nguyen-
dc.contributor.nonIdAuthorDo, Anh Tuan-
dc.contributor.nonIdAuthorZhou, Jun-
dc.contributor.nonIdAuthorKim, Tony Tae-Hyoung-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorBitline leakage equalization-
dc.subject.keywordAuthorcontent addressable memory-
dc.subject.keywordAuthorenergy efficiency improvement-
dc.subject.keywordAuthorultra-low voltage SRAM design-
dc.subject.keywordPlusSUBTHRESHOLD SRAM-
dc.subject.keywordPlusPROCESSOR-
dc.subject.keywordPlusOPERATION-
dc.subject.keywordPlusCIRCUITS-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordPlusMODE-
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