DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Bo | ko |
dc.contributor.author | Truc Quynh Nguyen | ko |
dc.contributor.author | Do, Anh Tuan | ko |
dc.contributor.author | Zhou, Jun | ko |
dc.contributor.author | Je, Minkyu | ko |
dc.contributor.author | Kim, Tony Tae-Hyoung | ko |
dc.date.accessioned | 2016-12-01T07:02:41Z | - |
dc.date.available | 2016-12-01T07:02:41Z | - |
dc.date.created | 2016-11-21 | - |
dc.date.created | 2016-11-21 | - |
dc.date.created | 2016-11-21 | - |
dc.date.created | 2016-11-21 | - |
dc.date.created | 2016-11-21 | - |
dc.date.issued | 2015-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.2, pp.441 - 448 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/214567 | - |
dc.description.abstract | This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 mu s. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V similar to 0.6 V by the proposed CAM-assisted circuit. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement | - |
dc.type | Article | - |
dc.identifier.wosid | 000349399800012 | - |
dc.identifier.scopusid | 2-s2.0-85027940188 | - |
dc.type.rims | ART | - |
dc.citation.volume | 62 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 441 | - |
dc.citation.endingpage | 448 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2014.2360760 | - |
dc.contributor.localauthor | Je, Minkyu | - |
dc.contributor.nonIdAuthor | Wang, Bo | - |
dc.contributor.nonIdAuthor | Truc Quynh Nguyen | - |
dc.contributor.nonIdAuthor | Do, Anh Tuan | - |
dc.contributor.nonIdAuthor | Zhou, Jun | - |
dc.contributor.nonIdAuthor | Kim, Tony Tae-Hyoung | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bitline leakage equalization | - |
dc.subject.keywordAuthor | content addressable memory | - |
dc.subject.keywordAuthor | energy efficiency improvement | - |
dc.subject.keywordAuthor | ultra-low voltage SRAM design | - |
dc.subject.keywordPlus | SUBTHRESHOLD SRAM | - |
dc.subject.keywordPlus | PROCESSOR | - |
dc.subject.keywordPlus | OPERATION | - |
dc.subject.keywordPlus | CIRCUITS | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | MODE | - |
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