Browse "RIMS Conference Papers" by Author Hyung-Cheol Shin
Showing results 1 to 60 of 60
| 25nm Bulk MOSFET with Floating Gate Spacer Hyung-Cheol Shin, Silicon Nanoelectronics Workshop, pp.12 - 13, 2000 |
| 45 nm baised spacer MOSFET Hyung-Cheol Shin, Silicon Nanoelectronics Workshop, pp.126 - 127, 2003 |
| 50 nm MOSFET with Floating Polysilicon Spacer Hyung-Cheol Shin, IEEE Silicon Nanoelectronics Workshop, pp.54 - 55, 2001 |
| 50 nm MOSFET with High-k Dielectric Sidewall Hyung-Cheol Shin, IEEE Silicon Nanoelectronics Workshop, pp.70 - 71, 2001 |
| A 2.4-GHz Fully Integrated CMOS Quadrature VCO Hyung-Cheol Shin, Asia Pacific-System on a Chip 2002, pp.207 - 210, 2002 |
| A 5-GHz Band I/Q Generator using a Self-Calibration Technique Beom-Sup Kim; Hyung-Cheol Shin, European Solid-State Circuit Conference, pp.807 - 810, 2002 |
| A Model of Thin Oxide Damage by Plasma Etching and Ashing Processes Hyung-Cheol Shin, Plasma Etch, pp.27 - 29, 1991 |
| A nano-structure Memory with SOI Edge channel and A nano dot Hyung-Cheol Shin, MNC(Microproceses and Nanotechnology Conference), pp.315 - 316, 1998 |
| A New Curvature-Compensated CMOS Bandgap Reference with Low Power Consumption Hyung-Cheol Shin, ITC-CSCC 2000, pp.612 - 614, 2000 |
| A new quantum dot formation process using wet etching of poly-Si along grain boundaries Hyung-Cheol Shin, MNC2000, pp.248 - 249, MNC, 2000-07 |
| A New SOI Inverter using Active Body-Bias Hyung-Cheol Shin, ITC-CSCC, pp.1457 - 1459, 1998 |
| A Nonvolatile Memory Using Nanocrystals Formed by Wet Etching Hyung-Cheol Shin, ICSMM 2000, pp.124 - 125, 2000 |
| A self-assembled silicon quantum dot transistor operation at room temperature Hyung-Cheol Shin, 1998 ASIAN SCIENCE SEMINAR, 1998 |
| A self-assembled silicon quantum dot transistor operation at room temperature Hyung-Cheol Shin, NPMS'98, 1998 |
| A self-assembled silicon quantum dot transistor operation at room temperature Hyung-Cheol Shin, Sound Quality Symposium Conference(SQS), 1998 |
| A Simple Technique to Measure Generation Lifetime in Partially Depleted SOI MOSFETS Hyung-Cheol Shin, 5th International Conference on VLSI and CAD, pp.55 - 59, 1997 |
| A Simple Wide-Band MIM Capacitor Model for RF Applications and the Effect of Substrate Grounded Shields Hyung-Cheol Shin, 2003 International Conference on Solid State Devices and Materials (SSDM 2003), 2003 |
| A Tri-Gate MOSFET with Gate-to-Source/Drain Non-overlapped Structure for 5 nm Regime Hyung-Cheol Shin, Silicon Nanoelectronics Workshop 2003, pp.32 - 33, 2003 |
| Accurate Four-Terminal RF MOSFET Model Accounting for the Short-Channel Effect in the Source-to-Drain Capacitance Hyung-Cheol Shin, SISPAD 2003, 2003 |
| Characteristics of P-channel Si Nano-crystal Memory Hyung-Cheol Shin, IEEE Region 10 Ionference, TENCON, pp.1140 - 1142, 1999 |
| Characteristics of P-channel Si Nano-crystal Memory with Tunneling Oxide Hyung-Cheol Shin, 99 ISDRS, pp.73 - 75, 1999 |
| Characteristics of Thermal Nitride Grown by IR Furnace Hyung-Cheol Shin, IUMRS-ICEM-98, pp.106 - 106, 1998 |
| Characterization of oxide Charging in a Magnetically Enhanced Rie Polysilicon Etcher Hyung-Cheol Shin, Proc. 11th International Syposium on Plasma Chemistry, pp.1534 - 1539, 1993 |
| Characterization of Process-Induced Damage During Aluminum Etching and Photoresist Ashing Hyung-Cheol Shin, International Wafer Level Reliability Workshop, pp.133 - 144, 1991 |
| Characterization of Thin Oxide Damage During Aluminum Etching and Photoresist Ashing Processes Hyung-Cheol Shin, International Symposium on VLSI Technology,Systems and Applications, pp.210 - 213, 1991 |
| Comparison of the characteristics of tunneling oxide and tunneling ON for P-channel Nano-crystal Memory Hyung-Cheol Shin, The 6th International Conference on VLSI and Cad(ICVC'99), pp.233 - 236, 1999 |
| DC and AC Characteristics of 10 nm T-Gate MOSFETs with Source/Drain-to-gate Non-Overlapped Structure Hyung-Cheol Shin, Silicon Nanoelectronics Workshop 2003, pp.24 - 25, 2003 |
| Device Characteristics of 25 nm MOSFET with Floating Side Gates Hyung-Cheol Shin, ICSMM 2000, pp.118 - 119, 2000 |
| Effect of Body Structure on Analog Performance of SOI NMOSFET's Hyung-Cheol Shin, IEEE SOI Conference, pp.61 - 62, 1998 |
| Effects of S/D non-overlap and high-κ dielectrics on nano CMOS design Hyung-Cheol Shin, ISDRS, pp.661 - 664, ISDRS, 2001-12 |
| Fabrication and Characterization of a Quantum Dot Flash Memory Hyung-Cheol Shin, 99 International Workshop on Advanced LSI's and Devices, pp.12 - 15, 1999 |
| Fabrication of siliocon Quantum Dots on Oxide and Nitride Hyung-Cheol Shin, MNC(Microproceses and Nanotechnology Conference), pp.136 - 137, 1998 |
| Factors Affecting Charge-up in a Magnetically Enhanced RIE Polysilicon Etcher Hyung-Cheol Shin, Proc. Electrochemical Society, pp.405 - 406, 1993 |
| Gate Oxide Damage by Plasma Oxide Deposition and Via RIE Hyung-Cheol Shin, American Vacuum Society Plasma Etch 1992 Symposium, 1992 |
| Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide Hyung-Cheol Shin, IEDM Technical Digest, pp.467 - 470, 1993 |
| Integrity of Gate Oxide on TFSOI Materials Hyung-Cheol Shin, Proc. IEEE International SOI Conference, pp.22 - 23, 1995 |
| Lateral Silicon Field Emission Devices using Electron Beam Lithography Hyung-Cheol Shin, Micoroprocesses and Nanotechnology'99, pp.134 - 135, 1999 |
| Materials, Device and Gate Oxide Integrith Evaluation of Simox and Bonded SOI Wafers Hyung-Cheol Shin, Proc. IEEE International SOI Conference, pp.143 - 145, 1995 |
| MOS Memory Using Si Nanocrystals Formed by Wet Etching of Poly-Silicon Along Grain Boundaries Hyung-Cheol Shin, 2000 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp.221 - 224, 2000 |
| On the large-signal CMOS modeling and parameter extraction for RF applications Hyung-Cheol Shin, SISPAD 2002, pp.67 - 70, SISPAD, 2002-09 |
| P-channel Nano Crystal Memory Hyung-Cheol Shin, 2000 China-Korea Joint Symposium on Semiconductor Physics and Device Application, pp.19 - 19, 2000 |
| Physical Modeling of Substrate Resistance in RF MOSFETs Hyung-Cheol Shin, Workshop on Compact Modeling at the 5th International Conference on Modeling and Simulation of Microsystems, pp.335 - 338, 2003 |
| Physical RF modeling of Junction Varactors Hyung-Cheol Shin, SSDM 2002, pp.418 - 419, 2002 |
| Plasma-Etching induced Damage to Thin Oxide Hyung-Cheol Shin, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp.79 - 83, 1992 |
| PMOS-based Si Nano-crystal Memory Hyung-Cheol Shin, Silicon nanoelectronics workshop, pp.10 - 11, 1999 |
| Process-Induced Charging Damage in PETEOS for Interlevel Dielectric Applications Hyung-Cheol Shin, International Symposium on Plasma Process-Induced Damage, pp.109 - 112, 1996 |
| Programming and Erasing Characteristics of P-channel Nano-crystal Memory Hyung-Cheol Shin, Semicon Korea Technical Symposium 2000, pp.5 - 10, 2000 |
| Quantized Canductance of a Gate-All-Around Silicon Quantum Wire Transistor Hyung-Cheol Shin, MNC(Microprocesses and Nanotechnology Conference, pp.150 - 151, 1998 |
| Recessed Channel(RC) SOI NMOSFET's with Self-Aligned Polysilicon Gate Formed on the RC Region Hyung-Cheol Shin, Proc. IEEE International SOI Conference, pp.122 - 123, 1996 |
| RF characteristics of 30 nm MOSFETs with non-overlapped source-drain to gate Hyung-Cheol Shin, Silicon Nanoelectronics Workshop 2002, 2002 |
| Silicon MOS Memory with self-aligned Quantum Dot on Narow Channel Hyung-Cheol Shin, ICVC99, pp.187 - 189, 1999 |
| Silicon nano-crystal memory with tunneling nitride Hyung-Cheol Shin, International Conference on Solid State Devices and Materials, pp.170 - 171, 1998 |
| Sub 4-nm Polyoxide Using ECR(Electron Cyclotron Resonance) N2O Plasma Oxidation Hyung-Cheol Shin, 2000 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp.25 - 30, 2000 |
| TFSOI Complementary BiCMOS Technology for Low Power RF Mixed-Mode Applications Hyung-Cheol Shin, IEEE Custom Integrated Circuits Conference, pp.35 - 38, 1996 |
| The P-Channel Si Nano-Crystal Memory Hyung-Cheol Shin, ICSICT 2001, pp.200 - 204, ICSICT, 2001-10 |
| Thickness and Other Defects on Oxide and Interface Reliability due to Plasma Processing Hyung-Cheol Shin, Proc. IEEE International Reliability Phys. Symp., pp.272 - 279, 1993 |
| Thin Oxide Damage by Plasma Etching and Ashing Processes Hyung-Cheol Shin, Proc. IEEE International Reliability Phys. Symp., pp.37 - 41, 1992 |
| Transient Behaviors in Partially Depleted Thin Film SOI Devices Hyung-Cheol Shin, Proc. IEEE International SOI Conference, pp.4 - 6, 1995 |
| Two Band Tunneling Currents in Dual-Gate CMOSFET with Ultrathin Gate Oxide Hyung-Cheol Shin, ICSMM 2000, pp.108 - 109, 2000 |
| Ultra thin oxide grown on polysilicon by ECR(Electron Cyclotron Resonance) N2O Plasma Hyung-Cheol Shin, 5th International Symposium on Plasma Process-Induced Damage 2000, no.2000, pp.133 - 136, 2000 |
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- 3,515 Conference
Date issued
- 324 2020 - 2023
- 961 2010 - 2019
- 1,104 2000 - 2009
- 918 1990 - 1999
- 155 1980 - 1989