Browse "RIMS Conference Papers" byAuthor1145

Showing results 1 to 60 of 60

1
A Complete Model for Glitch Analysis in Logic Circuits

Taewhan Kimresearcher, IEEE International ASIC/SOC Conference (ASIC), 2000

2
A low phase noise microwave oscillator using split ring resonators

Jung J.; Cho C.S.; Lee J.W.; Kim J.; Kim T.H.researcher, 36th European Microwave Conference, EuMC 2006, pp.95 - 98, 2006-09-10

3
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis

Taewhan Kimresearcher, IEEE International Conference on Computer-Aided Design (ICCAD), 2000

4
A Non-Zero Delay Model for Glitch Analysis in Logic Circuits

Taewhan Kimresearcher, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000

5
A Scheduling Algorithm for Conditional Resource Sharing

Taewhan Kimresearcher, IEEE International Conference on Computer-Aided Design (ICCAD), pp.84 - 87, 1991

6
A static estimation technique of power sensitivity in logic circuits

Kim T.researcher; Chung K.-S.; Liu C.L., 38th Design Automation Conference, pp.215 - 219, 2001-06-18

7
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability

Taewhan Kimresearcher, IEEE European Design and Test Conference (EDAC), pp.586 - 590, 1994

8
A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders

Taewhan Kimresearcher, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.313 - 316, 2000

9
A Verification of Memory Access Protocols in Behavioral Synthesis

Taewhan Kimresearcher, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000

10
Address assignment combined with scheduling in DSP code generation

Choi Y.; Kim T.researcher, 39th Annual Design Automation Conference, DAC'02, pp.225 - 230, 2002-06-10

11
Address code generation utilizing memory sharing in DSP processors

Kim T.researcher; Hong S., 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, v.2005, pp.579 - 582, 2005-08-07

12
Address Code Optimization using Code Scheduling for Digital Signal Processors

Taewhan Kimresearcher, IEEE International Symposium on Circuits and Systems, 2002

13
An Accurate Design Exploration of Arithmetic Circuits using Carry-Save-Adder Cells

Taewhan Kimresearcher, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.622 - 627, 2001

14
An accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save adder cells

Kim Y.-T.; Kim T.researcher, 43rd Midwest Circuits and Systems Conference (MWSCAS-2000), v.1, pp.338 - 341, 2000-08-08

15
An Efficient Binding Algorithm for Power Optimization based on Network Flow Method

Taewhan Kimresearcher, 6th Korea-Japan Joint Workshop on Algorithms and Computation, pp.9 - 14, 2001

16
An Efficient Data Path Synthesis Algorithm for Behavioral-level Power Optimization

Taewhan Kimresearcher, IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-294 - I-297, 1999

17
An Efficient Inverse Multiplier/Divider Architecture for Cryptography Systems

Taewhan Kimresearcher, IEEE International Symposium on Circuits and Systems (ISCAS), 2003

18
An Efficient Low-Power Binding Algorithm in High-Level Synthesis

Taewhan Kimresearcher, IEEE International Symposium on Circuits and Systems, 2002

19
An Integrated Approach to Data Path Synthesis for Low Power

Taewhan Kimresearcher, IEEE International ASIC/SOC Conference (ASIC), pp.125 - 129, 1999

20
An Integrated Data Path Synthesis Algorithm based on Network Flow Method

Taewhan Kimresearcher, IEEE Custom Integrated Circuits Conference (CICC), pp.615 - 618, 1995

21
Arithmetic Optimization using Carry-Save Adders

Taewhan Kimresearcher, ACM/IEEE Design Automation Conference (DAC), pp.442 - 447, 1998

22
Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications

Taewhan Kimresearcher, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000

23
Bus-invert coding for low-power I/O - A decomposition approach

Hong S.; Narayanan U.; Chung K.-S.; Kim T.researcher, 43rd IEEE Midwest Circuits and Systems Conference, 2000, v.2, pp.750 - 753, 2000-08-08

24
Coupling-aware high-level interconnect synthesis for low power

Lyuh C.-G.; Kim T.researcher; Kim K.-W., IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.609 - 613, 2002-11-10

25
DSP 내장형 시스템 설계에서 코드 스케쥴링을 이용한 주소 코드 최적화

김태환researcher, 한국정보고학회 학술 대회, pp.7 - 9, 2002

26
Enhanced Bus Invert Encoding for Low-Power

Taewhan Kimresearcher, IEEE International SYmposium on Circuits and Systems, 2002

27
Fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis

Um Junhyung; Kim Taewhanresearcher; Liu C.L., DAC 2000: 37th Design Automation Conference, pp.98 - 103, 2000-06-05

28
G-Vector: A New Model for Glitch Analysis

Taewhan Kimresearcher, IEEE International ASIC/SOC Conference (ASIC), pp.159 - 162, 1999

29
Layout-aware synthesis of arithmetic circuits

Um J.; Kim T.researcher, 39th Annual Design Automation Conference, DAC'02, pp.207 - 212, 2002-06-10

30
Layout-driven resource sharing in high-level synthesis

Um J.; Kim J.-H.; Kim T.researcher, IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.614 - 618, 2002-11-10

31
Low Power Bus Encoding with Crosstalk Delay Elimination

Taewhan Kimresearcher, IEEE ASIC/SOC Conference (ASIC), 2002

32
Memory access driven storage assignment for variables in embedded system design

Choi Y.; Kim T.researcher, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, pp.478 - 481, 2004-01-27

33
Memory Exploration utilizing Scheduling Effects in High-level Synthesis

Taewhan Kimresearcher, IEEE International Symposium on Circuits and Systems, 2002

34
Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design

Taewhan Kimresearcher, IEEE/ACM Design Automation Conference (DAC), pp.881 - 886, 2003

35
Optimal allocation of carry-save-adders in arithmetic optimization

Um Junhyung; Kim Taewhanresearcher; Liu C.L., Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99), pp.410 - 413, 1999-11-07

36
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications

Seo J.; Kim T.researcher; Dutt N.D., ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005, v.2005, pp.449 - 454, 2005-11-06

37
Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors

Taewhan Kimresearcher, IEEE/ACM Design Automation Conference (DAC), pp.125 - 130, 2003

38
Power Optimization in VLSI Design based on Efficient Network Flow Computations

Taewhan Kimresearcher, 6th Korea-Japan Workshop on ALgorithms and Computation, pp.3 - 8, 2001

39
Practical Issues on Behavioral Synthesis

김태환researcher, CAD 및 VLSI 설계 연구회 학술발표회 대회, pp.1 - 4, 1999

40
Profile-based optimal intra-task voltage scheduling for hard real-time applications

Seo J.; Kim T.researcher; Chung K.-S., Proceedings of the 41st Design Automation Conference, pp.87 - 92, 2004-06-07

41
Register Allocation for Dataflow Graphs with Conditional Branches and Loops

Taewhan Kimresearcher, IEEE European Design Automation Conference (Euro-DAC), pp.232 - 237, 1993

42
Resource-constrained low-power bus encoding with crosstalk delay elimination

Cha M.; Lyuh C.-G.; Kim T.researcher, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, pp.835 - 838, 2004-01-27

43
Resource-Constrained Low-Power Bus Encoding with Crosstalk Delay Elimination

Cha, Meeyoungresearcher; Kim, Taewhanresearcher, ACM/IEEE Asia Pacific Design Automation Conference (ASP-DAC), ACM/IEEE Asia Pacific Design Automation Conference (ASP-DAC), 2004-01-27

44
Utilization of Carry-Save Adders in Arithmetic Optimization

Taewhan Kimresearcher, IEEE International ASIC/SOC Conference (ASIC), pp.173 - 177, 1999

45
Utilization of Multiport Memories in Data Path Synthesis

Taewhan Kimresearcher, ACM/IEEE Design Automation Conference (DAC), pp.298 - 302, 1993

46
Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits

Taewhan Kimresearcher, IEEE International Conference on VLSI and CAD (VLSICAD), pp.89 - 94, 1999

47
WFA를 이용한 이미지 압축 알고리즘에 대한 분석

김태환researcher, 한국정보과학회 학술 대회, pp.727 - 729, 2002

48
고속 회로를 위한 비트 단위의 연산 최적화

김태환researcher, 한국정보과학회 학술 대회, pp.21 - 23, 2000

49
내장형 시스템에서의 암호 연산을 위한 효율적인 역원 연산기와 나눗셈 연산기의 구현

김태환researcher, 한국정보과학회 컴퓨터시스템연구회 학술대회 논문지(A), 2002

50
네트워크 플로우에 기반한 아키텍쳐 수준에서의 전력 최적화

김태환researcher, 한국정보과학회 학술 대회, pp.667 - 669, 2002

51
분산된 VLIW 구조에서의 최대전력 최소화 방법

김태환researcher, SOC Design Conference, 2002

52
상위 단계에서의 스케쥴링 효과를 이용한 메모리 탐색

김태환researcher; 서재원, 한국정보과학회 학술 대회, pp.3 - 5, 2002

53
스마트 카드에서의 Multiplicative Inverse연산을 위한 효율적인 하드웨어의 구현

김태환researcher, 한국정보처리학회 학술대회 논문지(A), 2002

54
연산회로 최적화를 위한 배선의 재배열

김태환researcher; 엄준형, 한국정보과학회 학술 대회, pp.661 - 663, 2002

55
저전력 소모를 위한 상위 수준의 효과적인 바인딩 알고리즘

김태환researcher, 한국정보과학회 학술 대회, pp.19 - 21, 2002

56
저전력 회로 설계를 위한 분할 버스-인버트 코딩 기법

김태환researcher, 한국정보과학회 학술대회, pp.27 - 29, 2000

57
저전력 회로를 위한 비트단위의 연산 최적화

김태환researcher, 한국정보과학회 학술대회, pp.16 - 19, 2002

58
최종 배선을 고려한 연산회로 합성

김태환researcher, 한국정보과학회 학술대회, pp.664 - 667, 2002

59
캐리-세이브 가신기를 이용한 지연시간 최적화를 위한 연산기 합성

김태환researcher, 한국정보과학회 학술 대회, pp.18 - 20, 2000

60
회로 속도 최소화를 위한 캐리-세이브 가산기 모델링 및 실험

김태환researcher, 한국 반도체 학술 대회 (KCS), 1999

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