Browse "School of Electrical Engineering(전기및전자공학부)" byTitle

Showing results 8561 to 8580 of 46610

8561
Area and error reduction techniques for on-chip temperature sensor = 온 칩 온도 센서의 면적과 오차 감소 기법link

Shin, Wong-Yu; 신원규; et al, 한국과학기술원, 2013

8562
Area and power efficient 10-bit column driver with interpolating DAC and push-pull amplifier for AMLCDs

Lee, H.-M.; Son, Y.-S.; Jeon, Y.-J.; Jeon, J.-Y.; Jung, S.-C.; Cho, Gyu-Hyeongresearcher, 2008 SID International Symposium, pp.889 - 891, 2008-05-20

8563
Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems

Kim, T.-H.; Park, In-Cheolresearcher, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.111 - 112, IEEE, 2008-03-21

8564
Area and power minimization in controller synthesis = 제어기 합성에서의 면적과 파워의 최소화link

Hong, Se-Kyoung; 홍세경; et al, 한국과학기술원, 1995

8565
Area efficient neuromorphic circuit based on stochastic computation

윤기원; 최수형; 신영수researcher, 한국반도체학술대회, 대한전자공학회, 2017-02-15

8566
Area efficient neuromorphic circuit based on stochastic computation

Yoon, Kiwon; Choi, Suhyeong; Shin, Youngsooresearcher, International SoC Design Conference, IEEE, IEIE, 2016-10-23

8567
Area efficient pipelined VLSI implementation of list sphere decoder

Lee J.; Park, Sin Chongresearcher, 2006 Asia-Pacific Conference on Communications, APCC, 2006-08-31

8568
Area optimization algorithms for FSM synthesis and FPGA technology mapping = FSM 합성과 FPGA 기술 매핑을 위한 면적 최적화 알고리즘link

Park, Sung-Soo; 박성수; et al, 한국과학기술원, 1995

8569
Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory

Jin, Y; Shihab, M; Jung, Myoungsooresearcher, MemoryForum, IEEE, 2014-06-14

8570
Area-Efficient and Reusable VLSI Architecture of Decision Feedback Equalizer of QAM Modem

Yu, Hyeongseok; Kim, Byung Wook; Cho, Yeon Gon; Cho, Jun Dong; Kim, Jea Woo; Lee, Jae Kon; Park, Hyuncheolresearcher; et al, Asia and South Pacific Design Automation Conference (ASP-DAC 2001), IEEE, 2001-01-30

8571
Area-Efficient Approach for Generating Quantized Gaussian Noise

Choi, Jaejoon; Jung, Jaehwan; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.7, pp.1005 - 1013, 2016-07

8572
Area-Efficient Architecture for Joint Estimation of Fine Timing and Interger Carrier Frequency Offsets

김태환; 박인철researcher, The 14th Korean Conference on Semiconductors (KCS 2007), 2007

8573
Area-efficient design of OFDM baseband receiver for DVB-T systems = DVB-T용 저면적 OFDM 기저대역 수신기 설계link

Lee, Hyun-Yong; 이현용; et al, 한국과학기술원, 2008

8574
Area-Efficient Digital Baseband Module for Bluetooth Wireless Communications

Park, In-Cheolresearcher; Shin, MCl; Park, SI; Lee, SW; Kang, SH, 한국반도체학술대회 (KCS), pp.441 - 442, 2002-02

8575
Area-efficient digital baseband module for Bluetooth wireless communications

Shin, M.-C.; Park, S.-I.; Lee, S.-W.; Kang, S.-H.; Park, In-Cheolresearcher, 2002 IEEE International Symposium on Circuits and Systems, v.5, pp.729 - 732, IEEE, 2002-05-26

8576
Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors

Paek, S.; Oh, J.; Chung, S.-H.; Kim, Lee-Supresearcher, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.1664 - 1667, IEEE, 2011-05-15

8577
Area-efficient high-performance reed-solomon decoder architecture for MLC SSD = 대용량 MLC SSD를 위한 고성능 저면적의 리드 솔로몬 복호기link

Yoo, Ho-Young; 유호영; et al, 한국과학기술원, 2012

8578
Area-efficient high-throughput low density parity check codes decoding architecture = 저면적 고성능 LDPC 코드 복호기에 대한 연구link

Kang, Se-Hyeon; 강세현; et al, 한국과학기술원, 2007

8579
Area-efficient low-power VLSI architectures for modern linear block codes = 최신 선형 블록 부호를 위한 저면적 저전력 하드웨어 설계link

Yoo, Hoyoung; 유호영; et al, 한국과학기술원, 2016

8580
Area-efficient memory-based architecture for FFT processing

Moon, S.-C.; Park, In-Cheolresearcher, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.5, 2003-05-25

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