Browse "School of Electrical Engineering(전기및전자공학부)" by Subject time-to-digital converter (TDC)

Showing results 1 to 15 of 15

1
A 0.22 ps(rms) Integrated Noise 15 MHz Bandwidth Fourth-Order Delta Sigma Time-to-Digital Converter Using Time-Domain Error-Feedback Filter

Yu, Wonsik; Kim, KwangSeok; Cho, Seong-Hwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.5, pp.1251 - 1262, 2015-05

2
A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications

Kim, Mi-Jo; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.58, no.8, pp.477 - 481, 2011-08

3
A 148fS(rms) Integrated Noise 4 MHz Bandwidth Second-Order Delta Sigma Time-to-Digital Converter With Gated Switched-Ring Oscillator

Yu, Wonsik; Kim, KwangSeok; Cho, SeongHwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.8, pp.2281 - 2289, 2014-08

4
A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2501 - 2512, 2019-09

5
A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

Kim, Dongin; Cho, Seonghwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.2, pp.232 - 236, 2019-02

6
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC

Kim, Jungho; Kim, Young-Hwa; Kim, KwangSeok; Yu, Wonsik; Cho, SeongHwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.7, pp.631 - 635, 2015-07

7
A Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction

Hwang, Chan woong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk, IDEC Journal of Integrated Circuits and Systems, v.9, no.4, pp.37 - 43, 2023-10

8
A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout

Kwon, Ji-Wook; Jin, Dong-Hwan; Kim, Hyeon-June; Hwang, Sun-Il; Shin, Min-Chul; Cheon, Jun-Ho; Ryu, Seung-Tak, IEEE SENSORS JOURNAL, v.16, no.14, pp.5524 - 5535, 2016-07

9
(A) digital phase-locked loop with phase detector quantization noise suppression techniques = 위상차 검출기의 양자화 잡음을 줄이는 방법을 사용한 디지털 위상고정루프link

Son, Woo-Kon; 손우곤; et al, 한국과학기술원, 2009

10
(A) synchronous clock generator using time-to-digital converter for mobile memory application = 모바일 메모리 어플리케이션을 위한 시간-디지털 변환기를 이용한 클럭 동기화 회로link

Kim, Mi-Jo; 김미조; et al, 한국과학기술원, 2010

11
An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 mu m(2) in 180-nm CMOS

Jung, Dong-Kyun; Seo, Jin-O; Cho, Seonghwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1638 - 1642, 2019-10

12
Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy

Shin, Sounghun; Jung, Yoontae; Kweon, Soon-Jae; Lee, Eunseok; Park, Jeong-Ho; Kim, Jinuk; Yoo, Hyung-Joun; et al, SENSORS, v.20, no.7, 2020-04

13
Fast-frequency offset cancellation loop using low-IF receiver and fractional-N PLL

Shin, S; Kim, K; Lee, Kwyro; Kang, SM, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.54, pp.272 - 276, 2007-03

14
Logarithmic resistance-to-digital converter for multi-level cell phase change memory readout = 멀티레벨 상변화 메모리의 readout을 위한 로그 저항-디지털 변환기link

Kwon, Ji-Wook; 권지욱; et al, 한국과학기술원, 2016

15
Wide input range, reconfigurable time-to-digital converter for electrical impedance spectroscopy applications = 임피던스 스펙트로스코피를 위한 넓은 입력 범위의 재구성 가능 시간-디지털 변환기link

Shin, Seongheon; Yoo, Hyung-Joun; et al, 한국과학기술원, 2017

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