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Showing results 1 to 6 of 6

1
A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS

Lee, Jae-Won; Lee, Woo-Jae; Cho, Seong-Hwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.59, no.1, pp.124 - 136, 2012-01

2
A high-frequency compensated crosstalk and ISI equalizer for multi-channel on-chip interconnect in 130-nm CMOS

Lee, Jaewon; Lee, Woojae; Cho, SeongHwan, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, v.2, no.2, pp.314 - 321, 2012-06

3
A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD

Kim, Hyo-Eun; Oh, Jie-Hwan; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.60, no.1, pp.21 - 25, 2013-01

4
Analysis and design of high-speed on-chip interconnect transceiver with crosstalk and ISI equalizer = 누전잡음과 부호간 간섭 등화기를 사용한 고속 칩상 인터컨넥트용 송수신기의 해석 및 설계link

Lee, Jae-Wan; 이재원; et al, 한국과학기술원, 2012

5
Capacitive coupled 3-Tap FFE and RC-filtered DDJ compensator for on chip global interconnects = 온 칩 데이터 전송을 위한 커패시터 결합 구조의 이퀄라이저와 데이터 의존성 지터 보상 회로link

Oh, Jie-Hwan; 오지환; et al, 한국과학기술원, 2012

6
Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme

Kim, Seongguk; Kim, Subin; Cho, Kyungjun; Shin, Taein; Park, Hyunwook; Lho, Daehwan; Park, Shinyoung; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.11, no.11, pp.1955 - 1970, 2021-11

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