Browse "School of Electrical Engineering(전기및전자공학부)" bySubjectJitter

Showing results 1 to 11 of 11

3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS

Yoon, Jong-Hyeok; Kwon, Kyeongharesearcher; Bae, Hyeon-Minresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.8, pp.2647 - 2658, 2020-08

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

Jung, Chongsoo; Lee, Dongil; Kim, Yong-Hun; Lee, Daewoong; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.12, pp.1972 - 1976, 2019-12

A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator

Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyoukresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.1, pp.298 - 309, 2021-01

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

Lee, Yongsun; Seong, Taeho; Yoo, Seyeon; Choi, Jaehyoukresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1192 - 1202, 2018-04

An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.12, pp.3466 - 3477, 2019-12

Building an Energy-efficient Uplink and Downlink Delay Aware TDM-PON System

Newaz, S.H.Shah; Jang, Min Seok; Mohammed, Alaelddin Fuad Yousif; Lee, Gyu Myoung; Choi, Jun Kyunresearcher, OPTICAL FIBER TECHNOLOGY, v.29, pp.34 - 52, 2016-05

Estimation of data-dependent jitter using single pulse analysis method in high-speed interconnects = 단일비트응답 분석을 통한 고속신호 전송선에서의 신호의존지터 예측link

Song, Eak-Hwan; 송익환; et al, 한국과학기술원, 2006

Jitter-tolerant I/O clock distribution network using chip and package hybrid interconnection = 칩과 패키지의 혼성 전송선을 이용한 저 지터 입출력 클럭 신호 분배의 설계 및 구현link

Chung, Dae-Hyun; 정대현; et al, 한국과학기술원, 2006

Low-noise PLL/DLL design and jitter/phase noise analysis = 저잡음 PLL/DLL 설계 및 지터/위상잡음 분석link

Lee, Joon-Suk; 이준석; et al, 한국과학기술원, 2002

Proposal of TSV-based 3D clock distribution networks and analysis = 관통 실리콘 비아 기반 3차원 클락 분배망에 관한 연구link

Kim, Da-Young; 김다영; et al, 한국과학기술원, 2012

Timing evaluation of MAC-layer error control on ARM9-based mobile embedded systems

Kim, C; Kang, K; Noh, DK; Ryu, J; Ma, JoongSooresearcher, TELECOMMUNICATION SYSTEMS, v.45, pp.329 - 337, 2010-12



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