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$.8 \um m$ CMOS를 이용한 1.485 Gb/s 병렬화기의 설계 = 1.485 Gb/s deserializer chip design using $.8 \um m$ CMOS for HDTV applicationlink

류지열; Ryoo, Ji-Yeoul; et al, 한국과학기술원, 1999

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