Browse "School of Electrical Engineering(전기및전자공학부)" by Author Pak, J.
Showing results 1 to 4 of 4
| A frequency tunable resonant clock distribution scheme using bond-wire inductor Lee, W.; Pak, J.S.; Pak, J.; Ryu, C.; Park, J.; Kim, Joungho, 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008, pp.24 - 26, IEEE, 2008-12-10 |
| Characterization of on-chip Interconnections and capacitive coupling effect on CMOS operational amplifier Shim ,Y.; Pak, J.; Kim, A.; Kim, Joungho, 20th International Zurich Symposium on Electromagnetic Compatibility, EMC Zurich 2009, pp.449 - 452, EMC, 2009-01-12 |
| Chip-package co-modeling & verification of noise coupling & generation in CMOS DC/DC buck converter Song, T.; Kim, J.; Pak, J.; Kim, Joungho, 20th International Zurich Symposium on Electromagnetic Compatibility, EMC Zurich 2009, pp.285 - 288, IEEE, 2009-01-12 |
| Noise generation, coupling, isolation, and EM raidaiton in high-speed package and PCB Kim, Joungho; Pak, J.; Park, J.; Kim, H., IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.5766 - 5769, IEEE, 2005-05-23 |
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