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Browse "School of Electrical Engineering(전기및전자공학부)" by Author Moon, Youngsuk

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Showing results 1 to 8 of 8

1	DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing Shin, Wongyu; Choi, Jungwhan; Jang, Jaemin; Suh, Jinwoong; Moon, Youngsuk; Kwon, Yongkee; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.3027 - 3040, 2016-10
2	Memory device supporting rank-level parallelism and memory system including the same Kim, Lee-Sup; Shin, Wongyu; Moon, Youngsuk; Kwon, Yongkee; Jang, Jaemin
3	Memory device supporting rank-level parallelism and memory system including the same Kim, Lee-Sup; Shin, Wongyu; Moon, Youngsuk; Kwon, Yongkee; Jang, Jaemin
4	Memory device supporting rank-level parallelism and memory system including the same Kim, Lee-Sup; Shin, Wongyu; Moon, Youngsuk; Kwon, Yongkee; Jang, Jaemin
5	Multiple Clone Row DRAM: A Low Latency and Area Optimizded DRAM Choi, Jungwhan; Shin, wongyu; Jang, Jaemin; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Lee-Sup, 2015 ACM/IEEE International Symposium on Computer Architecture, ACM SIGGRAPH and IEEE TCCA, 2015-06-15
6	Multiple clone row DRAM: A low latency and area optimized DRAM Choi, Jungwhan; Shin, Wongyu; Jang, Jaemin; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Lee-Sup, 42nd Annual International Symposium on Computer Architecture, ISCA 2015, pp.223 - 234, Institute of Electrical and Electronics Engineers Inc., 2015-06
7	Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation Shin, Wongyu; Choi, Jung Whan; Jang, Jaemin; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Hongsik; et al, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.7, pp.2213 - 2227, 2016-07
8	Rank-Level Parallelism in DRAM Shin, Wongyu; Jang, Jaemin; Choi, Jungwhan; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1274 - 1280, 2017-07

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