Browse "School of Electrical Engineering(전기및전자공학부)" by Author Chung, M.-K.
Showing results 1 to 10 of 10
| A prediction packetizing scheme for reducing channel traffic in transaction-level hardware/software co-emulation Lee, J.-G.; Chung, M.-K.; Ahn, K.-Y.; Lee, S.-H.; Kyung, Chong-Min, Design, Automation and Test in Europe, DATE '05, pp.384 - 389, DATE '05, 2005-03-07 |
| Cache miss-aware dynamic stack allocation Jang, S.-J.; Chung, M.-K.; Kim, J.; Kyung, Chong-Min, 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, pp.3494 - 3497, 123, 2007-05-27 |
| Cycle-accurate verification of AHB-based RTL IP with transaction-level system environment Shim, H.; Lee, S.-H.; Woo, Y.-S.; Chung, M.-K.; Lee, J.-G.; Kyung, Chong-Min, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, pp.135 - 138, 2007-04-26 |
| Improvement of compiled instruction set simulator by increasing flexibility and reducing compile time Chung, M.-K.; Kyung, Chong-Min, Proceedings - 15th IEEE International Workshop on Rapid Systems Prototyping, pp.38 - 44, RSP '04, 2004-06-28 |
| Improving lookahead in parallel multiprocessor simulation using dynamic execution path prediction Chung, M.-K.; Kyung, Chong-Min, 20th Workshop on Principles of Advanced and Distributed Simulation, PADS 2006, pp.11 - 18, 2006-05-24 |
| Low latency variable length coding scheme for frame memory recompression Lee, S.; Eum, N.; Chung, M.-K.; Kyung, Chong-Min, 2010 IEEE International Conference on Multimedia and Expo, ICME 2010, pp.232 - 237, IEEE, 2010-07-19 |
| Performance improvement of multiprocessor simulation by optimizing synchronization and communication Chung, M.-K.; Shim, H.; Kyung, Chong-Min, 16th Intetrnational Workshop on Rapid System Prototyping, RSP 2005, pp.158 - 164, RSP '05, 2005-06-08 |
| Reducing transaction-level modeling effort while retaining low communication overhead for HW/SW co-emulation system Kim, Y.-I.; Chung, M.-K.; Ki, A.; Kyung, Chong-Min, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, 2007-04-25 |
| System-level HW/SW Co-simulation framework for multiprocessor and multithread SoC Chung, M.-K.; Yang, S.; Lee, S.-H.; Kyung, Chong-Min, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), v.2005, pp.177 - 180, 2005-04-27 |
| System-level performance analysis of embedded system using behavioral C/C++ model Chung, M.-K.; Na, S.; Kyung, Chong-Min, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), v.2005, pp.188 - 191, 2005-04-27 |
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