Browse "School of Electrical Engineering(전기및전자공학부)" by Author Baek, Seung-Yeob
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| A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sunwoo; Choi, Michael; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1139 - 1148, 2018-04 |
| A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC Jang, Il-Hoon; Seo, Min-Jae; Kim, Mi-Young; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sun-Woo; Choi, Michael; et al, Symposium on VLSI Circuits, pp.C34 - C35, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-06 |
| A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS Moon, Kyoung-Jun; Kang, Hyun-Wook; Jo, Dong-Shin; Kim, Mi-Young; Baek, Seung-Yeob; Choi, Michael; Ko, Hyung-Jong; et al, 31st Symposium on VLSI Circuits, pp.C94 - C95, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-07 |
| Advanced addition-only digital error correction 기법을 포함하는 0.5μm CMOS 2.3V 1.2mW 12b 3MS/s SAR ADC의 설계 = A 2.3V 1.2mW 12b 3MS/s SAR ADC with advanced addition-only digital error correction in 0.5μm CMOSlink 백승엽; Baek, Seung-Yeob; et al, 한국과학기술원, 2012 |
| An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers Baek, Seung-Yeob; Lee, Jae-Kyum; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.60, no.9, pp.562 - 566, 2013-09 |
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