Browse "School of Electrical Engineering(전기및전자공학부)" by Author Asano, K
Showing results 1 to 3 of 3
| Patterning sub-30-nm MOSFET gate with i-line lithography Asano, K; Choi, Yang-Kyu; King, TJ; Hu, CM, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.48, no.5, pp.1004 - 1006, 2001-05 |
| Sub-50 nm p-channel FinFET Huang, XJ; Lee, WC; Kuo, C; Hisamoto, D; Chang, LL; Kedzierski, J; Anderson, E; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.48, no.5, pp.880 - 886, 2001-05 |
| Ultrathin-body SOI MOSFET for deep-sub-tenth micron era Choi, Yang-Kyu; Asano, K; Lindert, N; Subramanian, V; King, TJ; Bokor, J; Hu, CM, IEEE ELECTRON DEVICE LETTERS, v.21, no.5, pp.254 - 255, 2000-05 |
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