Browse "School of Electrical Engineering(전기및전자공학부)" by Author 237
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| 1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices Na, S.; Hwangbo, W.; Kim, J.; Lee, S.; Kyung, Chong-Min, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp.192 - 195, 2007-11-12 |
| 3D Geometry Graphics System Using Deferred Primitive Rendering with VLIW Geometry Processor Kyung, Chong-Min; Nam, S.J.; Kwon, Y.S.; Lee, J.H.; Im, Y.H., International Conference on Consumer Electronics(ICCE), 2000-06 |
| 3D Graphics System with VLIW Processor for Geometry Acceleration Kyung, Chong-Min; Jeon, Y.W.; Kwon, Y.S.; Im, Y.H.; Lee, J.H.; Nam, S.J.; Kim, B.W., IEEE Asia Pacific Conference on ASICs(AP-ASIC'2000), pp.367 - 370, 2000-08 |
| 3D-stacked L2 Cache Configuration for DVFS-enabled Processor to Minimize Overall Energy Consumption Kyung, Chong-Min, International Conference on Convergence and Hybrid Information Technology(ICHIT), International Conference on Convergence and Hybrid Information Technology(ICHIT), 2010 |
| 3차원 그래픽스 시뮬레이터 : SOFTGRA와 RACA 경종민; 어길수; 최훈규, 전자공학학술대회, pp.1528 - 1531, 1987 |
| 3차원 이미지의 광선 추적을 위한 가속화된 음영 검사방식 경종민; 최훈규, 대한전자공학회 논문집추계종합학술대회 , v.13, no.2, pp.643 - 646, 대한전자공학회, 1990 |
| 3차원 입체 모델링 및 랜더링 시스템의 개발 경종민; 최훈규; 박기현; 어길수; 김진한, 과학기술처 특정연구결과 발표회, pp.99 - 103, 1989 |
| A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs Kyung, Chong-Min; Yim, J.S., 36th Design Automation Conference(DAC), pp.766 - 771, 1999-06 |
| A Compiled-code Simulator with Reduced Edge Evaluation Yang, W.S.; Park, In-Cheol; Kyung, Chong-Min, APCHDL'98, pp.107 - 110, 1998-07 |
| A Double Structured Adaptive Finite Element Method for Semiconductor Device Analysis Kyung, Chong-Min; Choi, K.; Han, M.K.; Hahn, S.Y., The 3rd Biennial IEEE Conference on Electromagnetic Field Computation, 1988-12 |
| A Fast Heuristic for Optimal CMOS Functional Cell Layout Generation Kyung, Chong-Min; Kwon, Y.J., International Symposium on Circuits and Systems, 1988-06 |
| A Fast Rate Estimation For Rate-Distortion-Optimized H.264 Intra Encoder Design 경종민, IEEK Summer Conference 2010, IEEK Summer Conference 2010, 2010 |
| A Fast Sine/Cosine Generator with Pipelined CORDIC and Table Lookup Method Shin, M.C.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.281 - 284, 1998-10 |
| A Floorplanning Using Rectangular Voronoi Digranm and force-Directed Block shaping Kyung, Chong-Min; Choi, S.G., ICCAD-1991, 1991-04 |
| A Global router Using Simulated Annealing Applicable to Power and Ground Router Kyung, Chong-Min; Choi, S.G., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1988-11 |
| A Graph Matching Algorithm for Circuit Partitioning and Placement in Rectilinear Region and Nonplanar Surface Park, In-Cheol; Kyung, Chong-Min, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.182 - 186, 대한전자공학회, 1988 |
| A Hardware Accelerator for Phong Illumination Model in 3-Dimentional Grahpics Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, HUMANTECH, pp.277 - 285, 1999 |
| A Hardware Accelerator for Scanline Interpolation and Hidden Surface Removal Kyung, Chong-Min; Eo, K.S.; Kim, S.S., International Conference on VLSI, 1989-08 |
| A Hardware Accelerator for the Specular Intensity of Phong Illumination Model in 3-Dimensional Kwon, Y. S.; Park, In-Cheol; Kyung, Chong-Min, ASP-DAC'2000, pp.559 - 564, 2000-01 |
| A Heuristic Algorithm for Minimal Area CMOS Cell Layout Kyung, Chong-Min; Kwon, Y.J., Proceedings of 1987 Joint Technical Conference on Circuits and Systems, pp.111 - 116, 1987-07 |
| A high-performance 2-D inverse transform architecture for the H.264/AVC decoder Hwangbo, W.; Kim, J.; Kyung, Chong-Min, 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, pp.1613 - 1616, 2007-05-27 |
| A Hybrid Shadow testing Scheme During Ray Tracing Kyung, Chong-Min; Eo, K.S.; Choi, H.K., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1988-11 |
| A Methodology for Compatible Microprocessor Design 박인철; 성광수; 홍세경; 공배선; 이승종; 최훈; 경종민, 대한전자공학회 추계종합학술대회, v.19, no.2, pp.993 - 996, 대한전자공학회, 1996 |
| A Multi-Threading MPEG Processor with Variable Issue Modes Yang, W.S.; Kim, H.S.; Park, In-Cheol; Shin, M.C.; Kyung, Chong-Min, International Conference on VLSI and CAD(ICVC'99), pp.545 - 548, 1999-10 |
| A New Design Rule Checker Based on Corner Checking and Bit Mapping Kyung, Chong-Min; Eo, K.S., International Symposium on Circuits and Systems, pp.1289 - 1292, 1985-06 |
| A New Floorplanning Algorithm Using Force-Directed Block Shaping Kyung, Chong-Min; Choi, S.G., JTC-CSCC91, 1991-07 |
| A New Layout Scheme for Macro Cells Kyung, Chong-Min; Lee, P.H., International Conference on VLSI and CAD, 1991-10 |
| A New Parallel Hardware Architecture for Fast Polygon Rendering Kyung, Chong-Min; Bae, S.O.; Song, G.S., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1990-12 |
| A New Pin Assignment Algorithm for Building Block Layout Kyung, Chong-Min; Choi, S.G., JTC-CSCC, 1992-07 |
| A new RTL debugging methodology in FPGA-based verification platform Yang, S.; Shim, H.; Yang, W.; Kyung, Chong-Min, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp.180 - 183, 2004-08-04 |
| A New State Encoding Algorithm by the Construction of Hypercube Kyung, Chong-Min; Park, S.S., International Conference on VLSI and CAD, 1993-11 |
| A Novel Bus Interface and Motion Compensation Architecture for H.264/AVC with Reduced Memory Access Kyung, Chong-Min; Kim, Jaemoon; Hwangbo, Woong, 제16회 한국반도체학술대회(KCS), 2009 |
| A P-Channel Schottky-Clamped MOSFET Utilizing Boron-Doped Sidewall Oxide Kim, Choong Ki; Kyung, Chong-Min; Oh, C.S., International Symposium on VLSI Technology,Systems and Applications, pp.250 - 253, 1985-05 |
| A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ICCD'99(International Conference on Computer Design), pp.243 - 248, 1999-10 |
| A Relaxation-and-Reduction Algorithm for Optimal Transistor Sizing Kyung, Chong-Min; Kwon, Y.J., International Conference on VLSI and CAD, 1991-10 |
| A Router for Symmetrical FPGA Based on Exact Routing DEnsity Evaluation Kim, Taewhan; Kyung, Chong-Min; Eum, Nak-Woong, IEEE International Conference on Computer-Aided Design, pp.137 - 143, 2001-11 |
| A Two-Dimensional Geometry Processor for DRC Applications Kyung, Chong-Min; Eo, K.S., 1987 IEEE Region 10 Conference, pp.266 - 270, 1987-08 |
| ACCENT : A CISC-Type Configurable Processor Core Chang, Y.S.; Park, B.I.; Yang, W.S.; Oh, H.S.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.195 - 198, 1998-10 |
| Adaptive Cluster Growth(ACG) : A New algorithm for Circuit Packing in Rectilinear Region Kyung, Chong-Min; Widder, J.; Mlynski, D.A., European Design Automation Conference, 1990-03 |
| Adaptive Prediction and Rollback Scheme for Synchronizing Simulator and Accelerator for mixed-level Simulation Kyung, Chong-Min; Lee, Jae-Gon; Shim, Heejun, IFIP VLSI-SoC Conference, 2005 |
| Advanced Techniques for Multiprocessor Simulation Kyung, Chong-Min; Chung, Moo-Kyoung, International SoC Design Conference(ISOCC) 2004, pp.388 - 391, 2004-10 |
| Algorithms for Finding Optimal Module Orientations in Macro Cell Placement Kyung, Chong-Min; Jeong, J.C.; Kim, S.S., International Conference on VlSi and CAD, 1991-10 |
| An 0(n)-time Standard Cell Placement Algorithm Using Constained Multi-Stage Graph Model Kyung, Chong-Min; Cho, H.G., International Symposium on Circuits and Systems, 1988-06 |
| An 0(n3logn)-Heuristic for Microcode Bit Optimization Kyung, Chong-Min; Hong, S.K.; Park, I.C., International Conference on Computer-Aided Design, pp.180 - 183, 1990-11 |
| An Accurate Evaluation of Routing Density for Symmetrical FPGAs Kim, Taewhan; Kyung, Chong-Min; Eum, Nak-Woong, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.51 - 55, 2001-03 |
| An Analytic Approach to Three Layer Channel Routing Kyung, Chong-Min; Lee, P.H., APCCAS, 1992 |
| An early block type decision method for intra prediction in H.264/AVC Do, J.; Na, S.; Kyung, Chong-Min, 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009, pp.97 - 101, 2009-10-07 |
| An Efficient Algorithm for Optimal PLA Folding Kyung, Chong-Min; Yang, Y.Y., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1988-11 |
| An Efficient Algorithm for Optimal PLA Folding Kyung, Chong-Min; Yang, Y.Y., International Symposium on Circuits and Systems, 1989-05 |
| An Efficient Approach to Functional Verification of Complex Processors Lee, S.J.; Won, N.R.; Cho, H.C.; Park, B.I.; Chang, Y.S.; Park, S.I.; Park, In-Cheol; et al, International Conference on Chip Technology, 1998-04 |
| An Efficient Collision Detection Algorithm for Computer Animation Kyung, Chong-Min; Choi, H.K.; Kim, H.J., JTC-CSCC91, 1991-07 |
| An Efficient Data Storage Scheme for 3-D Scene Rendering Kyung, Chong-Min; Choi, H.K.; Eo, K.S., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1988-11 |
| An efficient routing algorithm for symmetrical FPGAs using reliable cost metrics Eum, N.-W.; Park, I.; Kyung, Chong-Min, 13th Workshop on Circuits and Systems in Karuizawa, no.3, pp.829 - 838, 2000-04-24 |
| An Efficient Scheduling Algorithm for High-Level Synthesis 박인철; 경종민, The First Semiconductor Workshop for Young Engineers, pp.59 - 62, 1991 |
| An evolutionary strategy for the global placement of macro cells Kyung, Chong-Min; Kraus, Peter V.; Mlynski, Dieter A., 1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4), v.3, pp.1668 - 1671, 1990-05-01 |
| An Implementation of Pipelined Rijndael with SystemC and Co-emulation with iPROVE Kyung, Chong-Min; Lee, Jae-Gon; Yang, Woo-Seung; Ki, Ando, SNUG(Synopsys Users Group) Korea 2003, 2003-05 |
| An Integrated Framework for Multi-Core Architectures with 3D-Stacked Memory Kyung, Chong-Min, International Conference on Convergence and Hybrid Information Technology(ICHIT), International Conference on Convergence and Hybrid Information Technology(ICHIT), 2010 |
| An Interative PC-Based Logic Design Capture and Simulation System Kyung, Chong-Min; Choi, H.K.; Kim, S.S.; Ahn, Y.S., 1987 IEEE Region 10 Conference, pp.261 - 265, 1987-08 |
| Automatic generation of software/hardware co-emulation interface for transaction-level communication Kim, Y.-I.; Ahn, K.-Y.; Shim, H.; Yang, W.; Kwon, Y.-S.; Ki, A.; Kyung, Chong-Min, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), v.2005, pp.196 - 199, 2005-04-27 |
| Automatic translation of behavioral testbench for fully accelerated simulation Kim, Y.-I.; Kyung, Chong-Min, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, pp.218 - 221, 2004-11-07 |
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