Browse "School of Electrical Engineering(전기및전자공학부)" byAuthor1380

Showing results 1 to 60 of 223

1
3-D adaptive simulation of thermal oxidation process

Cho, Byung Jinresearcher; Yoon, SH; Lee, JH; Won, TY; Kim, JC; Lee, DH, 26th European Solid State Device Research Conf. (ESSDERC), pp.0 - 0, 1996-09-09

2
A comparative study of multiple and single pulse laser annealing for ultrashallow boron junction formation

Cho, Byung Jinresearcher; Poon, D; Lu, YF; Bhat, M; See, A, Ultra-Shallow Junctions-2003 Workshop, pp.0 - 0, 2003-04-27

3
A comparison study of high-density MIM capacitors with ALD HfO2-Al2O3 laminated, sandwiched and stacked dielectrics

Cho, Byung Jinresearcher; Ding, SJ; Hu, H; Zhu, C; Kim, SJ; Li, MF; Chin, A; et al, Conference on Solid State and Integrated Circuit Technology (ICSICT), pp.0 - 0, 2004-10-18

4
A novel approach for integration of dual metal gate process using ultra thin aluminum nitride buffer layer

Cho, Byung Jinresearcher; Park, CS; N. Balasubramanian, N; Kwong, DL, Symposium on VLSI Technology, pp.149 - 149, 2003-06-10

5
A novel floating gate engineering technique for improved data retention of flash memory devices

Pu, J.; Chan, D.S.H.; Cho, Byung Jinresearcher, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, pp.839 - 842, 2008-10-20

6
A novel Hafnium Carbide Metal Gate Electrode for NMOS Device Application

Cho, Byung Jinresearcher; Hwang, WS; Shen, C; Wang, XP; Chan, DSH, 2007 Symposium on VLSI Technology, pp.156 - 157, 2007-06-12

7
A strong temperature dependent hole direct tunneling current in p+ gate/pMOSFET with ultra-thin gate oxide

Cho, Byung Jinresearcher; Ang, CH; Ling, CH; Cheng, ZY, Extended Abstract of the 200 International Conf. on Solid State Devices and Materials (SSDM), pp.254 - 254, 2000-08-28

8
A study of quasi-breakdown mechanism in ultra thin gate oxide under various types of stress

Cho, Byung Jinresearcher; Guan, H; Xu, Z; Li, MF; He, YD, Materials Research Society (MRS) 1999 Fall Meeting Symp., pp.0 - 0, 1999-11-29

9
A study of quasi-breakdown mechanism in ultra-thin gate oxide by using DCIV technique

Cho, Byung Jinresearcher; Guan, H; Li, MF; He, YD; Xu, Z; Dong, Z, the 7th International Symp. on the Physical and Failure Analysis of Integrated Circuits, pp.81 - 81, 1999-07-05

10
A systematic study of high-K interpoly dielectric structures for floating gate flash memory devices

Cho, Byung Jinresearcher; Zhang, L; He, W; Chan, DSH, IEEE 2nd International conference on memory technology and design, pp.223 - 226, 2007-03-07

11
Adhesion Characteristic of Graphene Synthesized on Cu

Yoon, T.; Shin, W.C.; Mun, J.H.; Cho, Byung Jinresearcher; Kim, Taek-Sooresearcher, Materials Research Society Fall Meeting, Materials Research Society (MRS), 2013-12-01

12
Adhesion Energy and Etching-Free Renewable Transfer of Graphene As-Grown on Copper

Yoon, Taesik; Shin, Woo Cheol; Kim, Taek Yong; Mun, Jeong Hun; Cho, Byung Jinresearcher; Kim, Taek-Sooresearcher, The Electrochemical Society Meeting, ECS, 2012-10-07

13
ALD (HfO2)x(Al2O3)1-x high-K gate dielectrics for advanced MOS devices application

Cho, Byung Jinresearcher; Yu, HY; Wu, N; Yeo, C; Joo, MS; Li, MF; Zhu, C, 2nd International Conference on Materials for Advanced Technologies, pp.562 - 562, 2003-12-11

14
ALD of HfLaO and AlLaO for Flash Memory Device Application

조병진researcher; He, W, The 4th Korean ALD Workshop, pp.99 - 115, 2008-05-30

15
Analysis of charge trapping and breakdown mechanism in high-K dielectrics with metal gate electrode using carrier separation

Cho, Byung Jinresearcher; Loh, WY; Joo, MS; Li, MF; Chan, DSH; Kwong, DL, International Electron Device Meeting (IEDM), pp.0 - 0, 2003-12-08

16
Annealing behavior of a double MeV implanted silicon

Cho, Byung Jinresearcher; Cho, NH; Huh, TH; Jang, YT; Ro, JS; Lee, KH; Kim, JC, International Conf. on Ion Implantation Technology, pp.661 - 661, 1997-05-22

17
Anomalous Diffusion Phenomena in Two-Step Rapid Thermal Diffusion of Phosphorus

Kim, Choong Ki; Cho, Byung Jinresearcher, SPIE's Technical Symposium on Microelectronic Processing, pp.180 - 191, 1990

18
Application of graphene for analog and digital electronics

Cho, Byung Jinresearcher, The 3rd KOREA-FRANCE Joint Symposium 2014, 이화CNRS 국제공동연구소, 양자메타물질연구센터, 이화여자대학교 물리학과 BK21플러스 사업팀, LIA/GRDI/IPCMS-CNRS (France), 2014-06-25

19
Application of High-ĸ dielectrics to MIM capacitors for RF/analog CMOS Devices

Cho, Byung Jinresearcher; Kim, SJ, SEMICON Korea 2006 SEMI Technology Symposium, pp.0 - 0, 2006-02-08

20
Band offset FinFET-based URAM (unified-RAM) built on SiC for multi-functioning NVM and capacitorless 1T-DRAM

Han, J.-W.; Ryu, S.-W.; Kim, S.; Kim, C.-J.; Ahn, J.-H.; Choi, S.-J.; Kyu, J.C.; et al, Symposium on VLSI Technology Digest of Technical Papers, VLSIT 2008, pp.200 - 201, IEEE, 2008-06-17

21
Behavior of Effective Work Function in Metal/High-K Gate Stack under High Temperature Process

Cho, Byung Jinresearcher; Joo, MS; Chi, DZ; Balasubramanian, N; Kwong, DL, Conf. on Solid State Devices and Materials (SSDM), pp.0 - 0, 2004-09-14

22
Bipolar current stressing and electrical recovery of quasi-breakdown in thin gate oxides

Cho, Byung Jinresearcher; Loh, WY; Li, MF; Xu, Z, 8th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.59 - 59, 2001-07-09

23
Channel mobility behaviour in high-K/metal gate NMOSFETs

Cho, Byung Jinresearcher; Mathew, S; Bera, LK; Balasubramanian, N; Joo, MS, 2nd International Conference on Materials for Advanced Technologies, pp.516 - 516, 2003-12-11

24
Channel-width effect on hot-carrier degradation in NMOSFETs with recessed-LOCOS isolation structure

Cho, Byung Jinresearcher; Yue, JMP; Chim, WK; Qin, WH; Chan, DSH; Kim, YB; Jang, SA, Proc. of the 7th International Symp. on the Physical and Failure Analysis of Integrated Circuits (I, pp.94 - 94, 1999-07-05

25
Characterization of Ultrathin Plasma Nitrided Gate Dielectrics in PMOSFET for 0.18µm Technology and Beyond

Cho, Byung Jinresearcher; Tan, SS; Ang, CH; Lek, CM; Chen, T; See, A; Chan, L, 9th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.254 - 254, 2002-07-08

26
Charge transfer phenomena in Graphene Cdse/ZnS quantum dot system and their application

Klekaachev, AV; Asselberghs, I; N.Kuznetsov, S; Cantoro, M; Mun, JH; Cho, Byung Jinresearcher; Hofkens, J; et al, Graphene Week 2012, 2012-06

27
Chemical Analysis and Thermal Curing Effects of CVD graphene during transfer process

Hong, Seul Ki; Cho, Byung Jinresearcher, Graphene 2012, 2012-04

28
Chemical and Electrical Analysis of CVD Grown Graphene During Layer Transfer Process From Metal to Dielectric Substrate

Hong, Seul Ki; Song, Seung Min; Cho, Byung Jinresearcher, Nature conference - Graphene : The Road to Applications, Nature Publishing Group, 2011-05

29
Correlation between interface traps and gate laeakage in ultra-thin silicon dioxide

Cho, Byung Jinresearcher; Loh, WY; Li, MF; Lek, CM; Yong, YF; Joo, MS, 9th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.246 - 246, 2002-07-08

30
Cubic structured HfLaO dielectrics for MIM capacitor for RF IC applications

Zhang, L.; He, W.; Chan, D.S.H.; Cho, Byung Jinresearcher, International Symposium on Silicon Nitride, Silicon Dioxide, and Emerging Dielectrics - 215th Meeting of the Electrochemical Society, v.19, pp.615 - 623, 2009-05-24

31
Damage free etching of RuO2 in O2/He plasma

Cho, Byung Jinresearcher; Hwang, WS; Bliznetsov, VN; Chan, DSH; Yoo, WJ, 28th International Symposium on Dry Process, pp.0 - 0, 2006-11-29

32
Demonstration of Ge pMOSFETs with 6 A EOT using TaN/ZrO2/Zr-cap/n-Ge(100) Gate Stack Fabricated by Novel Vacuum Annealing and in-situ Metal Capping Method

Shin, Yunsang; Chung, Wonil; Seo, Yujin; Lee, Choong-Ho; Sohn, Dong Kyun; Cho, Byung Jinresearcher, 2014 Symposium on VLSI Technology, VLSI Symposium, 2014-06-11

33
Demonstration of High Performance PMOSFETs Using Si/SixGe1-x/Si Quantum Wells with High-k/Metal Gate Stacks and Uniaxial Strain Additivity for 22 nm T

Cho, Byung Jinresearcher; Suthram, S; Majhi, P; Sun, G; Kalra, P; Harris, R; Choi, KJ, International Electron Device Meeting (IEDM) 2007, pp.0 - 0, 2007-12-01

34
Demonstration of Low Vt NMOSFETs Using Thin HfLaO in ALD TiN/HfSiO Gate Stack

Cho, Byung Jinresearcher; Park, CS; Song, SC; Bersuker, G; Alshareef, HN; Ju, BS; Majhi, 2006 International Conference on Solid State Devices and Materials (SSDM 2006), pp.0 - 0, 2006-09-12

35
Dependence of Electrical and Mechanical Properties of Graphene on Different Dielectric Substrates

Cho, Byung Jinresearcher; Song, Seung Min, 2010 Material Research Society Spring Meeting, 2010 Material Research Society Spring Meeting, 2010-04-07

36
Dependence of graphene properties on dielectric under-layers

Cho, Byung Jinresearcher; Song, Seung Min, 30th International Conference on the Physics of Semiconductors, 30th International Conference on the Physics of Semiconductors, 2010-07-29

37
Design of IGBT gate drive with SOA consideration

Cho, Byung Jinresearcher; Luo, J; Liang, YC, IEEE Power Electronics Drives and Energy systems for Industrial Growth (PEDES)' 98, pp.307 - 307, 1998-11-30

38
Design of lateral OGBT protection circuit for smart power integration

Cho, Byung Jinresearcher; Luo, JY; Liang, YC, Proc. of 1999 International Conf. on Power Electronics and Drive System, pp.0 - 0, 1999-07-27

39
Dopant Segregated Pt and Ni-Germanide Schottky S/D p-MOSFETs with Strained Si-SiGe channel, 211th Electrochemical Society Meeting, SYMPOSIUM E1

Cho, Byung Jinresearcher; Zang, H; Chua, CK; Loh, WY, Electrochemical Society Meeting, SYMPOSIUM E1, 2007

40
Doping of Al-catalyzed Vapor-liquid-solid Grown Si Nnanowires

Cho, Byung Jinresearcher; Whang, SJ; Lee, SJ; Yang, WF; Zhu, HC; Gu, HL; Liew, YF, 2007 MRS Spring Meeting, pp.0 - 0, 2007-04-09

41
Double spacer LOCOS process with shallow recess of silicon for 0.20 um isolation

Cho, Byung Jinresearcher; Jang, SA; Song, TS; Pyi, SH; Kim, JC, International Conf. on Solid State Devices and Materials (SSDM), pp.40 - 40, 1996-08-26

42
Dramatic Improvement of high-K Gate Dielectric Reliability by Replacing Metal Gate Electrode with Mono-Layer Graphene

Park, Jong Kyung; Song, Seung Min; Mun, Jeong Hun; Cho, Byung Jinresearcher, 2012 Symposium on VLSI Technology, 2012-06

43
Dramatic increases of dielectric constant Al2O3 by very light doping of La and thermal treatment and its application to flash memory device

Park, JK; Lee, Seok-Heeresearcher; Lee, KH; Pyi, SH; Cho, Byung Jinresearcher, 제 19회 한국반도체학술대회, 고려대학교, 한국반도체산업협회,한국반도체연구조합, 2012-02-17

44
Dual Metal and fully silicided metal gate processes with tunable workfunction

Cho, Byung Jinresearcher, International NanoElectronics Materials Conference, pp.0 - 0, 2004-03-05

45
Dual metal gate CMOS with tunable work function and high-K gate dielectrics

Cho, Byung Jinresearcher, 1st International Workshop on Nanoscale Semiconductor Devices, pp.0 - 0, 2004-05-18

46
Dual Metal Gate Process by Metal Substitution of Dopant-Free Polysilicon on High-K Dielectric

Cho, Byung Jinresearcher; Park, CS; Hwang, WS; Loh, WY; Tang, LJ; Kwong, DL, Symposium on VLSI Technology, pp.48 - 49, 2005-06-14

47
Dual metal gate process scheme for wide range work function modulation and reduced Fermi level pinning

Cho, Byung Jinresearcher; Park, CS; Lwin, PW; Wong, SY; Pu, J; Hwang, WS, 3rd International Conference on Materials for Advanced Technologies, pp.41 - 41, 2005-07-03

48
Effect of additional low temperature RTA on ultra-shallow p+-n junction formation

Cho, Byung Jinresearcher; Lee, KH; Oh, JG; Kim, JC, 11th International Conf. on Ion Implantation Technology, pp.634 - 637, The Korea Society of Applied Physics, 1997-05-22

49
Effect of electron-beam lithography on thin gate oxide reliability

Cho, Byung Jinresearcher; Chong, PF; Chor, EF; Joo, MS, 8th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.55 - 55, 2001-07-09

50
Effect of in-situ P doped polysilicon on gate oxide (I) - yield degradation

Cho, Byung Jinresearcher; Lim, JU; Park, YJ; Kim, JC; Choi, SH, 41st Spring Meeting of the Japan Society of Applied Physics and Related Societies, pp.664 - 664, 1994-03-28

51
Effect of in-situ P doped polysilicon on gate oxide (II) - Process condition dependence

Cho, Byung Jinresearcher; Lim, JU; Park, YJ; Kim, JC; Choi, SH, 41st Spring Meeting of the Japan Society of Applied Physics and Related Societies, pp.664 - 664, 1994-03-28

52
Effect of Ti deposition temperature on TiSi2 orientation and its thermal instability in heavility doped Si

Cho, Byung Jinresearcher; Park, BH; Yu, SH; Kim, JC, 1996 Spring Meeting of Materials Research Society of Korea, pp.0 - 0, 1996-05-17

53
Effects of Cu diffusion on MOSFET electrical properties

Cho, Byung Jinresearcher; Zhu, C; Yoo, WJ; Tan, DPP; Lim, SY, 18th International VLSI Multilevel Interconnection Conf. (VMIC), pp.0 - 0, 2001-11-28

54
Effects of Low Energy Nitrogen Plasma on the Removal of HfSiON

Cho, Byung Jinresearcher; Hwang, WS; Yoo, WJ; Chan, DSH, AVS 53rd International Symposium, pp.0 - 0, 2006-11-12

55
Effects of Post-Decoupled-Plasma-Nitridation Annealing of Ultra-Thin Gate Oxide

Cho, Byung Jinresearcher; Lek, CM; Loh, WY; Ang, CH; Lin, W; Tan, YL; Zhen, JZ; et al, 9th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.0 - 0, 2002-07-08

56
Electrical and Physical Properties of ALD HfLaO for CMOS Device Application

Cho, Byung Jinresearcher; He, W; Kim, SJ; Kim, YS, Material Research Society 2008 Spring Meeting, 2008-03-26

57
Electrical and physical properties of Si1-xGex/HfO2/Si MOS-capacitors

Cho, Byung Jinresearcher; Wu, N; Zhu, C; Balasubramanian, N; Yeo, CC; Joo, MS; Yu, HY, 2nd International Conference on Materials for Advanced Technologies, pp.535 - 535, 2003-12-11

58
Electrical evaluation of laser annealed junctions by Hall measurement

Cho, Byung Jinresearcher; Poon, DCH; Tan, LS; Bhat, M; Chan, L, 2nd International Conference on Materials for Advanced Technologies, pp.578 - 578, 2003-12-11

59
Electrical Properties of CMOS Devices with Cu Local Interconnects

Cho, Byung Jinresearcher; Xie, H; Yoo, WJ; Zhu, C; Lim, SY; Tan, D; Lai, D, 8th International Conference on Dielectrics & Conductors for ULSI Multilevel Interconnection (DCMIC), pp.0 - 0, 2002-02-25

60
Energy band engineered unified-RAM (URAM) for multi-functioning 1T-DRAM and NVM

Han, J.-W.; Ryu, S.-W.; Kim, S.; Kim, C.-J.; Ahn, J.-H.; Choi, S.-J.; Choi, K.J.; et al, IEEE International Electron Devices Meeting, IEDM 2008, IEEE, 2008-12-15

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