Browse "School of Electrical Engineering(전기및전자공학부)" byAuthor1108
Showing results 1 to 60 of 179
| 8-Pipeline-Stage 32-bit Embedded Processor Using Dual Clock Domain Song, Jinook; Lee, Youngjoo; Kim, Bongjin; Park, In-Cheolresearcher, IEEE International SoC Design Conference (ISOCC 2011) Chip Design Contest, IEEE, 2011-11-17 |
| 8051 호환 마이크로컨트롤러의 설계 이용석; 이성원; 강형주; 김진석; 박인철researcher, 대한전자공학회 추계종합학술대회, v.32, no.2, pp.173 - 176, 대한전자공학회, 2000-11-25 |
| A 2.6Gb/s 1.56mm2 near-optimal MIMO detector in 0.18um CMOS Kim, T.-H.; Park, In-Cheolresearcher, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, pp.1 - 4, CICC 2010, 2010-09-19 |
| A 2048-Point FFT Processor Based on Twiddle Factor Table Reduction Kim , JH; Park, In-Cheolresearcher, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips 2007), pp.351 - 364, IEEE, 2007-04 |
| A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications Woo, R.; Cho,i S.; Sohn, J.-H.; Song, S.-J.; Bae, Y.-D.; Yoon, C.-W.; Nam, B.-G.; et al, 2003 Digest of Technical Papers, 2003-02-09 |
| A 24-bit floating-point audio DSP controller supporting fast exponentiation Lee, S.-W.; Kang, H.-J.; Park, In-Cheolresearcher, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.2, IEEE, 2003-05-25 |
| A 32-bit Multithreaded RISC for Embedded Real-time Application 배영돈; 박인철researcher, 한국반도체학술대회 (KSC), pp.249 - 250, 2002-02 |
| A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors Bae, Y.-D.; Park, In-Cheolresearcher, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC, pp.583 - 586, 2004-10-03 |
| A 5-GHZ self-calibrated I/Q clock generator using a quadrature LC-VCO Ahn, H.K.; Park, In-Cheolresearcher; Kim, B., Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.1, pp.797 - 800, IEEE, 2003-05-25 |
| A 50mbps double-binary turbo decoder for wiMAX based on bit-level extrinsic information exchange Kim, J.-H.; Park, In-Cheolresearcher, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp.305 - 308, IEEE, 2008-11-03 |
| A 6Gbps SSD Controller using Low-complexity and Time-interleaved BCH Encoder/Decoder Lee, Youngjoo; Yoo, Hoyoung; Yoo, Injae; Park, In-Cheolresearcher, IEEE International SoC Design Conference (ISOCC 2011) Chip Design Contest, IEEE, 2011-11-17 |
| A 80/20MHz 160mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications Yoon, C.-W.; Woo, R.; Kook, J.; Lee, S.-J.; Lee, K.; Bae, Y.-D.; Park, In-Cheolresearcher; et al, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.142 - 143441, 2001-02-05 |
| A Compiled-code Simulator with Reduced Edge Evaluation Yang, W.S.; Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, APCHDL'98, pp.107 - 110, 1998-07 |
| A Fast Reed-Solomon Product-Code Decoder Without Redundant Computations Park, In-Cheolresearcher; Lee, HY, 2003 SoC Design Conference(SDC), pp.829 - 832, 2003-11-05 |
| A fast Reed-Solomon product-code decoder without redundant computations Lee, H.-Y.; Park, In-Cheolresearcher, 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, v.2, IEEE, 2004-05-23 |
| A Fast Sine/Cosine Generator with Pipelined CORDIC and Table Lookup Method Shin, M.C.; Park, B.I.; Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, '98 ASIC ON PROCEEDINGS, pp.281 - 284, 1998-10 |
| A Fault-Tolerant Architecture of Embedded Processors for Electric Vehicle Systems 공병용; 김봉진; 송진욱; 유인재; 박인철researcher, 대한전자공학회 추계학술대회, 대한전자공학회, 2011-11-26 |
| A Fixed-Point MPEG Audio Processor for Low Frequency Operation Yi, YS; Park, In-Cheolresearcher, International Symposium on Circuits and Systems (ISCAS), pp.300 - 303, 2002-05-26 |
| A Fully-intergrated reader system for Mobile UHF RFID 이영주; 김태환; 박강우; 임고은; 박인철researcher, 제 17회 한국반도체학술대회, 2010-02 |
| A Graph Matching Algorithm for Circuit Partitioning and Placement in Rectilinear Region and Nonplanar Surface Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.182 - 186, 대한전자공학회, 1988 |
| A Hardware Accelerator for Phong Illumination Model in 3-Dimentional Grahpics Kwon, Y.S.; Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, HUMANTECH, pp.277 - 285, 1999 |
| A Hardware Accelerator for the Specular Intensity of Phong Illumination Model in 3-Dimensional Kwon, Y. S.; Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, ASP-DAC'2000, pp.559 - 564, 2000-01 |
| A High-Speed and Low-Latency Reed-solomon Decoder Based on a Dual-Line Structure Kang, HJ; Park, In-Cheolresearcher, International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.3180 - 3183, 2002-05-13 |
| A High-Speed and Low-Latency Reed-Solomon Decoder Based on a Dual-Line Structure 강형주; In-Cheol Park, 한국반도체학술대회(KCS), pp.233 - 234, 2002-02 |
| A hybrid delta-sigma modulator with adaptive calibration Shim, J.H.; Park, In-Cheolresearcher; Kim, B., Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.1, IEEE, 2003-05-25 |
| A Low-Power Variable Length Decoder Based on Successive Decoding of Short Codewords Lee, SW; Park, In-Cheolresearcher, CAD 및 VLSI 설계연구회 학술발표대회, pp.157 - 162, 대한전자공학회, 2000-05 |
| A LOW-POWERr VARIABLE LENGHT DECODER BASED ON SUCCESSIVE DECODING OF SHOFT CODEWORDS Lee, SW; Park, In-Cheolresearcher, International Symphosium on Circuits and Systems(ISCS), pp.582 - 585, IEEE, 2001-05 |
| A Methodology for Compatible Microprocessor Design 박인철researcher; 성광수; 홍세경; 공배선; 이승종; 최훈; 경종민researcher, 대한전자공학회 추계종합학술대회, v.19, no.2, pp.993 - 996, 대한전자공학회, 1996 |
| A Multi-Threading MPEG Processor with Variable Issue Modes Yang, W.S.; Kim, H.S.; Park, In-Cheolresearcher; Shin, M.C.; Kyung, Chong-Minresearcher, International Conference on VLSI and CAD(ICVC'99), pp.545 - 548, 1999-10 |
| A New Single-Clock Flip-Flop for Half-Swing Clocking Kwon, Y.S.; Park, B.I.; Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, ASP-DAC'99, pp.117 - 120, 1999-01 |
| A novel trace-pipelined binary arithmetic coder architecture for JPEG2000 Rhu, M.; Park, In-Cheolresearcher, 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009, pp.243 - 248, 2009-10-07 |
| A programmable turbo decoder for multiple 3G wireless standards Shin, M.-C.; Park, In-Cheolresearcher, IEEE International Solid-State Circuits Conference(ISSCC 2003), 2003-02-09 |
| A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders Park, B.I.; Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, ICCD'99(International Conference on Computer Design), pp.243 - 248, 1999-10 |
| A Reverse Caculation for Low Power MAX-Log-MAP Turbo Decoder Choi, HM; Park, In-Cheolresearcher, The 12th Korean Conference on Semiconductors, pp.27 - 28, 2005-02 |
| A scalable and programmable sound synthesizer Kim, T.-H.; Lee, Y.-J.; Park, In-Cheolresearcher, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, pp.1855 - 1858, IEEE, 2009-05-24 |
| A scalable SIMD digital signal processor for high quality multifunctional printer systems Kang, HJ; Choi, Y; Kim, K.; Park, In-Cheolresearcher; Kim, JW; Lee, EH; Gahang, GS, Proceedings of SPIE-IS and T Electronic Imaging - Color Imaging X: Processing, Hardcopy, and Applications, v.5667, pp.448 - 456, International Society for Optical Engineering (SPIE), 2005-01-17 |
| A single-chip programmable platform based on a multithreaded processor and configurable logic clusters Bae, Y.-D.; Park, S.-I.; Yi, Y.; Park, In-Cheolresearcher, 2002 IEEE International Solid-State Circuits Conference, v.1, pp.336 - 337, 2002-02-03 |
| A unified parallel radix-4 turbo decoder for Mobile WiMAX and 3GPP-LTE Kim, J.-H.; Park, In-Cheolresearcher, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, pp.487 - 490, 2009-09-13 |
| ACCENT : A CISC-Type Configurable Processor Core Chang, Y.S.; Park, B.I.; Yang, W.S.; Oh, H.S.; Park, In-Cheolresearcher; Kyung, Chong-Minresearcher, '98 ASIC ON PROCEEDINGS, pp.195 - 198, 1998-10 |
| An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking Park, In-Cheolresearcher; Shin, MC; Kang , SH, IDEC Conference 2002 Summer, pp.119 - 122, 2002 |
| An area-efficient iterative modified-booth multiplier based on self-timed clocking Shin, M.-C.; Kang, S.-H.; Park, In-Cheolresearcher, IEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001), pp.511 - 512, 2001-09-23 |
| An Efficient Approach to Functional Verification of Complex Processors Lee, S.J.; Won, N.R.; Cho, H.C.; Park, B.I.; Chang, Y.S.; Park, S.I.; Park, In-Cheolresearcher; et al, International Conference on Chip Technology, 1998-04 |
| An Efficient Binding Algorithm for Data-Path Synthesis 박인철researcher, IEEE Korea Section Student Paper Contest, pp.1 - 15, 1991 |
| An Efficient Scheduling Algorithm for High-Level Synthesis 박인철researcher; 경종민researcher, The First Semiconductor Workshop for Young Engineers, pp.59 - 62, 1991 |
| An O(n3logn)-heuristic for microcode bit optimization Hong, SK; Park, In-Cheolresearcher; Kyung, CM, 1990 IEEE International Conference on Computer-Aided Design - ICCAD-90, pp.180 - 183, 1990-11-11 |
| Analysis of Optimal Fault-Tolerant Adder Schemes for Wide Bit-Width Processors 공병용; 박인철researcher, 대한전자공학회 하계종합학술대회, 대한전자공학회, 2012-06-29 |
| Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000 Rhu, M.; Park, In-Cheolresearcher, 2009 IEEE International Conference on Image Processing, ICIP 2009, pp.2665 - 2668, 2009-11-07 |
| Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems Kim, T.-H.; Park, In-Cheolresearcher, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.111 - 112, IEEE, 2008-03-21 |
| Area-Efficient Architecture for Joint Estimation of Fine Timing and Interger Carrier Frequency Offsets 김태환; 박인철researcher, The 14th Korean Conference on Semiconductors (KCS 2007), 2007 |
| Area-Efficient Digital Baseband Module for Bluetooth Wireless Communications Park, In-Cheolresearcher; Shin, MCl; Park, SI; Lee, SW; Kang, SH, 한국반도체학술대회 (KCS), pp.441 - 442, 2002-02 |
| Area-efficient digital baseband module for Bluetooth wireless communications Shin, M.-C.; Park, S.-I.; Lee, S.-W.; Kang, S.-H.; Park, In-Cheolresearcher, 2002 IEEE International Symposium on Circuits and Systems, v.5, pp.729 - 732, IEEE, 2002-05-26 |
| Area-efficient memory-based architecture for FFT processing Moon, S.-C.; Park, In-Cheolresearcher, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.5, 2003-05-25 |
| ARM 프로세서용 부동 소수점 보조 프로세서 개발 김태민; 신명철; 박인철researcher, 대한전자공학회 정기총회 및 추계종합학술대회 , pp.232 - 235, 대한전자공학회, 1999 |
| ARM7 호환 32비트 RISC 프로세서의 설계 및 검증 배영돈; 서보익; 이용석; 박인철researcher, 대한전자공학회 추계종합학술대회, pp.416 - 420, 대한전자공학회, 1999 |
| Array address translation for SDRAM-based video processing applications Kim, H; Park, In-Cheolresearcher, Visual Communications and Image Processing 2000, v.4067, pp.922 - 931, 2000-06-20 |
| Bluetooth 기저대역 모듈을 위한 USB 인터페이스의 설계 Park , SI; Park, In-Cheolresearcher, 한국반도체학술대회 (KCS), pp.255 - 256, 2002-02 |
| C-Based Design Methodology 박인철researcher, 대한전자공학회 CAD 및 VLSI 설계 연구회 학술발표회, pp.993 - 996, 대한전자공학회, 1997 |
| C-based RTL design verification methodology for complex microprocessor Yim, JS; Hwang, YH; Park, CJ; Choi, H; Yang, WS; Oh, HS; Park, In-Cheolresearcher; et al, Proceedings of the 1997 34th Design Automation Conference, pp.83 - 88, 1997-06-09 |
| Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters Lee, J.-S.; Park, In-Cheolresearcher, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp.236 - 239, IEEE, 2008-05-18 |
| Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters Lee, Y.; Park, In-Cheolresearcher, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, pp.1464 - 1467, IEEE, 2010-05-30 |
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