Browse "School of Electrical Engineering(전기및전자공학부)" by Author 심성보
Showing results 1 to 4 of 4
| Full-chip level estimation of temperature-dependent leakage power 최수형; 심성보; 신영수, 한국반도체학술대회, 대한전자공학회, 2017-02-15 |
| Identifying redundant inter-cell margins and its application to technology mapping 이유종; 심성보; 신영수, 한국반도체학술대회, 대한전자공학회, 2014-02-25 |
| Physical design and mask synthesis for directed self-assembly lithography = 직접 자기조립 리소그라피를 위한 회로 설계 및 마스크 합성 연구link Shim, Seongbo; 심성보; et al, 한국과학기술원, 2016 |
| Reducing routing congestion and chip area by post placement optimization utilizing redundant inter-cell margin 정우현; 심성보; 신영수, 한국반도체학술대회, 대한전자공학회, 2015-02-10 |
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