A method for estimating EMI reduction and its application on a Fractional-N PLL based SSCG design = EMI감소를 평가하는 방법 및 이를 응용하는 Fractional-N PLL기반의 SSCG설계에 대한 연구

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dc.contributor.advisorLee, Sang-Gug-
dc.contributor.advisor이상국-
dc.contributor.authorNguyen, Duy Bien Yen-
dc.contributor.authorNguyen, Duy Bien Yen-
dc.date.accessioned2015-04-23T08:12:40Z-
dc.date.available2015-04-23T08:12:40Z-
dc.date.issued2013-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=566047&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/197773-
dc.description학위논문(박사) - 한국과학기술원 : 정보통신공학과, 2013.8, [ vi, 64 p. ]-
dc.description.abstractAn accurate estimation of Electromagnetic interference (EMI) reduction is realized by a theoretical analysis. The proposed analysis allows to estimating EMI reduction in a straightforward manner from the predetermined modulation index and noise injection. The degradation in EMI reduction is directly correlated with the amount of injected noise in a SSCG. A statistic analysis of the state-of-the-art Fractional-N Phase Locked Loop (PLL) based SSCGs is presented to prove the validity of the proposed analysis. The estimation is matched to measurement results taken from the state-of-the-art Fractional-N PLL based SSCGs. Furthermore, a design example of N-fractional Phase Locked Loop (PLL) based SSCG is presented to prove the validity of the proposed analysis. The estimation of EMI reduction in the designed N-fractional PLL based SSCG is finalized by the loop bandwidth trade-off of noise injection. The measured EMI reduction of a designed N-fractional PLL based SSCG is matched to the proposed estimation value. For further study on the bandwidth trade-off issue, a new architecture of N-fractional PLL based SSCG without bandwidth trade-off is proposed.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectEMI reduction-
dc.subject스프레드 스펙트럼 클록 발생기-
dc.subject삼각 변조 프로필-
dc.subject주파수 변조-
dc.subjectEMI 감소-
dc.subjectFractional-N 주파수기-
dc.subjectfrequency modulation-
dc.subjecttriangular modulation profile-
dc.subjectspread spectrum clock generator-
dc.subjectFractional-N PLL-
dc.subjectCMOS-
dc.titleA method for estimating EMI reduction and its application on a Fractional-N PLL based SSCG design = EMI감소를 평가하는 방법 및 이를 응용하는 Fractional-N PLL기반의 SSCG설계에 대한 연구-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN566047/325007 -
dc.description.department한국과학기술원 : 정보통신공학과, -
dc.identifier.uid020055914-
dc.contributor.localauthorLee, Sang-Gug-
dc.contributor.localauthor이상국-
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