Modeling and measurement analysis of through silicon via (TSV) and defects = 실리콘 관통 비아 및 결함의 모델링과 측정 분석

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As a solution to limitlessly growing demand on high speed, wide system bandwidth, and low power consumption, through silicon via (TSV) based 3-dimensional integrated circuit (3D-IC) has brought another era of technology evolution. In 3D-IC, semiconductor chips with different functions are stacked in multiple layers and integrated as a whole system. Signals are vertically transmitted through TSVs, which enables the shortest paths between the chips and maximized count by passing through the silicon substrates. Despite the attractive benefits of the technique, handling semiconductor wafers requires highly precise control in fabrication and integration.One of the major challenges in TSV technique is to reduce signal loss in silicon substrate. TSVs are formed by copper filling in the etched spaces in silicon substrate with insulation layer that electrically isolates TSVs from the substrate. In high frequency ranges, signals couple through the insulation layer, causing degradation of signal transmission of the system. Additionally, since TSV based 3D-ICs are developed for application to commercialized products, the fabrication cost has to be minimized before proceeding to mass production. As solutions to the mentioned problems, various types of TSVs have been developed, such as, through silicon lining via (TSLV), through organic lining via (TOLV) and coaxial organic lining via (COLV). Each type of TSVs has unique structure and characteristics, which needs to be analyzed for appropriate applications according to the purposes. As the system design aims for higher speed and wider bandwidth, the order of TSV count is increasing up to thousands. In order to fit in such large number of TSVs in a limited space of silicon substrate, diameter and pitch of TSVs have to be minimized. The scale-down of TSVs results in decreased yield level caused by various types of defects. The precision in existing fabrication process is insufficient to reach the acceptable level of reliabili...
Advisors
Kim, Joung-Horesearcher김정호
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2013
Identifier
566520/325007  / 020114241
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2013.8, [ vi, 39 p. ]

Keywords

Through Silicon Via (TSV); 결함 검출; 등가 회로 모델; 3차원 집적 회로; 관통 실리콘 비아; Defect Analysis; 3-dimensional integrated circuit (3D-IC); Equivalent circuit model

URI
http://hdl.handle.net/10203/196692
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=566520&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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