Unsupervised feature learning by pre-route simulation of auto-encoder behavior model

Abstract

This paper assesses the feasibility of deep learning hardware by demonstrating an auto-encoder behavior model on pre-route simulation. Many recent deep learning literature has focused on learning high-level abstraction of unlabeled raw data by unsupervised fea-ture learning. However, the computation complexity and the slowness of the learning pro-cess due to large amounts of training data required better algorithms to be developed. Addi-tionally, using FPGAs rather than serial computing CPUs could efficiently overcome these computational drawbacks. However, the design effort for FPGA implementations of deep learning algorithms remains challenging and time consuming. In order to check the feasibil-ity of designing deep learning architectures on FPGA, we designed a behavior model of auto-encoder and performed pre-route simulation using VerilogHDL in MODELSIM. We successfully obtained a cycle-accurate result of the first hidden layer’s parameters. More specifically, we extracted latent representations of the hidden layer using the Kyoto natural images and remodeled MNIST image databases. Also, we evaluated the classification per-formance on MNIST by using the pre-route of the single auto-encoder and SOFTMAX classifier. This paper shows how pre-route simulation can help the designing process of unsupervised learning algorithms on hardware by providing the cycle-accurate result.