Dynamic reconfiguration of 3D-stacked heterogeneous cache system3차원 이종 캐쉬 시스템의 실시간 동적 동작 방법

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Non-volatile memory technologies (NVMs) such as Magnetic RAM (MRAM) and Phase-Change RAM (PCRAM) have the low leakage power and high cell density characteristics when compared to conventional SRAM or DRAM memory technologies. Three-dimensional (3-D) integration technology enables stacking disparate memory technologies including non-volatile memory layers as well as conventional SRAM memory layers onto chip-multiprocessors (CMPs). However, the high power density resulting from multiple (memory) die stacking may lead to the temperature-related problems in reliability (e.g., NBTI), power, performance, and cooling cost. Especially, NVMs suffer from longer write latency, higher write energy consumption, and lower write enduramce compared with conentional memory technologies. In this dissertation, techniques, algorithms, and architectures (e.g., DVFS, power gating, cache partitioning, and heterogeneous SRAM/MRAM cache architecture) are proposed to address the power-related issue and write access overheads in 3D-stacked hybrid SRAM/NVMs cache onto CMP architectures, especially focusing on the power, the performance, and memory lifetime. In Chapter 1, the challenges of emerging technologies such as NVMs and system integration are introduced. Chapter 2 reviews the related works. Chapter 3 focuses on temperature-related power issue in 3D multi-core sys-tems with hybrid SRAM/MRAM L2 cache. In Chapter 3, we proposed a runtime thermal management method for CMPs with 3-D stacked hybrid SRAM/MRAM L2 cache. The proposed method combines dynamic cache management such as resource allocation, way-based power gating, and data migration with dynamic voltage and frequency scaling (DVFS) of processing cores in a temperature and energy-aware manner. Chapter 4 focuses on the design exploration of 3-D stacked non-uniform hybrid SRAM/MRAM L2 cache architecture (NUCA) using on-chip network to mitigate the interconnection problem. In Chapter 4, we investigates the problem of partitioning s...
Advisors
Kyung, Chong-Minresearcher경종민
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2014
Identifier
591813/325007  / 020047970
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2014.8, [ ix, 86 p. ]

Keywords

3D integration; 네트워크 온 칩; NUCA 캐쉬 아키텍처; 런타임 알고리즘; 캐쉬 리소스 분배; 동적 전압/주파수 제어; Hybrid cache architecture; Reconfiguration; DVFS (Dynamic Voltage Frequency Scaling); Cache partitioning; Runtime algorithm; NUCA (Non-uniform cache architecture); NoC; 삼차원 집적기술; 이종 캐쉬 아키텍처; 재설정

URI
http://hdl.handle.net/10203/196578
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=591813&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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