In-depth study of reliability for charge-trap-type flash memory devices = 전하포획형 플래시 메모리 소자의 신뢰성에 관한 심층 연구

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This dissertation focuses on finding innovative solutions in charge trap type flash memory device using high-κ materials in order to overcome the limitations of conventional floating-gate type Flash memory device as a result of fast shrinking device geometries. For that purpose, improvement of memory characteristics for charge trap type cell has been accomplished by engineering of the charge trap layer, the blocking oxide, the gate electrode, and the channel layer. For charge trap layer engineering, a charge-trap-type flash memory with a La2O3 doped Si3N4 charge trapping layer is demonstrated. An ultrathin La2O3 layer is inserted in the middle of a Si3N4 layer, followed by high temperature annealing to mix the two layers. The La2O3 doped Si3N4 layer, irrespective of Si3N4 deposition processes, is found to provide deep charge trapping sites, resulting in an excellent pre/post-cycling retention property and high reliability. For blocking oxide engineering, the use of lightly La doped aluminum oxide blocking layer for TANOS memory devices is investigated. The dielectric constant of Al2O3 is significantly increased through the addition of a very small amount of La into Al2O3 followed by a high temperature post-deposition annealing process. The retention property and reliability of the charge trap flash memory devices fabricated through the proposed method are greatly improved due to the increased κ-value of the Al2O3 blocking oxide with no sacrifice of the bandgap, as well as a reduced low-field leakage. For gate electrode engineering, a graphene layer is applied as the gate material of a charge trap type memory device. An excellent charge retention property and multi-bit operation of a CTF device, the most critical issues in CTF devices, were successfully demonstrated by using a graphene electrode. As the mono-atomic layer graphene electrode eliminates mechanical stress in the blocking oxide, significant enhancement of the data retention property and progr...
Advisors
Cho, Byung-Jinresearcher조병진
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2014
Identifier
568590/325007  / 020105082
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2014.2, [ Ⅵ, 163 p. ]

Keywords

charge trap type flash memory; 정션리스; 초기 문턱전압 불안정 현상; 게이트 전극; 전하차단막; 전하포획막; high-κ dielectrics; charge trap layer; blocking oxide; gate electrode; polysilicon channel; junctionless; transient threshold voltage shift; 전하포획형 플래쉬 메모리; 고유전막; 데이터 보존 특성; 신뢰도

URI
http://hdl.handle.net/10203/196554
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=568590&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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