Integrated management method of non-volatile memory with a DRAM buffer for lifetime and performance improvement

Abstract

In a conventional computing system, DRAM is used for the main memory, and a Hard Disk Drive (HDD) is exploited as a secondary storage. In a large-scale computing era, they have suffered from large power consumption, scalability wall, and slow speed on random pattern. These problems can be overcome by new memory technologies, such as Phase Change RAM (PRAM) and NAND flash memory, which have non-volatility, high scalability, and random access characteristics. However, the endurance and performance issues are arisen as new challenges. In this dissertation, we will address these limitations by designing two integrated management schemes of emerging memory technologies with a DRAM buffer: adaptive wear-leveling algorithm and workload-adaptive combination of write buffer and FTL.

- Adaptive Wear-Leveling Algorithm for PRAM Main Memory with a DRAM Buffer: Phase Change RAM (PRAM) is a candidate to replace DRAM main memory due to its low idle power consumption and high scalability. However, its latency and endurance have generated problems in fulfilling its main memory role. The latency can be treated with a DRAM buffer, but the endurance problem remains with three critical points that need to be improved despite the use of previous algorithms. First, previous DRAM buffering schemes do not consider write count distribution. Second, swapping and shifting are performed statically. Finally, swapping and shifting are loosely coupled with a DRAM buffer. As a remedy to these observations, we propose an adaptive wear-leveling algorithm that consists of three novel schemes, for PRAM main memory with a DRAM buffer. The PRAM-aware DRAM buffering scheme reduces write count and prevents skewed writing by considering write count and clean data. The adaptive multiple swapping and shifting scheme makes write count even with dynamic operation timing and the number of swapping pages being based on the workload pattern. The DRAM buffer-aware swapping and shifting scheme reduces unneces...