Frequency synthesizer is utilized to provide a local oscillator (LO) frequencies in wireless transceiver system. Among the many performance parameters of frequency synthesizers, the phase noise and spur are the most important factors that determine the spectral purity. Since the spectral purity often characterizes the performance of the overall wireless communication system such as sensitivity in the receiver and spectral mask compliance in the transmitter, aggressive approaches to mitigate the issues on the phase noise and spur are required. This dissertation addresses the severe degradation of phase noise characteristics due to the quantization noise in fractional-N synthesis and the source of spur emission particularly upon the electromagnetic interference (EMI) in SoC system.
Considering first the quantization noise in $\Delta\Sigma$ frequency synthesizer, it aggravates the out-of-band phase noise performance due to its high-pass noise shaping characteristic. In order to alleviate this issue, three distinct solutions are addressed; i.e. I. An area efficient high order discrete-time loop filter, II. Glitch-free low-supply 0.5 step fractional frequency divider, and III. Fast and power-efficient gain calibration algorithm for quantization noise-cancelling DAC.
In addition, the EMI from the digital circuit in SoC is prone to turn into a single tone frequency, and consequently threatens the reliability of data processing in an RF/analog circuit, especially the spur in wireless transceiver system. In order to suppress the EMI, a spread-spectrum clock generator (SSCG) with a delay-based direct digital phase modulation (DDPM) method is proposed. The proposed SSCG relieves the radiated EMI power level in a given bandwidth by decentralizing the concentrated spectrum using a continuous non-linear up/down modulation; i.e. Hershey-Kisses profile.