DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Seung Han | ko |
dc.contributor.author | Kang, Kyungsu | ko |
dc.contributor.author | Kyung, Chong-Min | ko |
dc.date.accessioned | 2015-04-08T08:08:04Z | - |
dc.date.available | 2015-04-08T08:08:04Z | - |
dc.date.created | 2014-07-09 | - |
dc.date.created | 2014-07-09 | - |
dc.date.created | 2014-07-09 | - |
dc.date.issued | 2015-03 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.23, no.3, pp.520 - 533 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/195980 | - |
dc.description.abstract | Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. 3-D integration technology using through-silicon vias enables stacking disparate memory technologies (e. g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The use of hybrid memories as an on-chip cache can take advantage of the best characteristics that each technology offers. However, the inherent high power density and heat removal limitation in 3-D integrated circuits may incur temperature-related problems. In this paper, we propose a runtime thermal management method for CMPs with the 3-D stacked hybrid SRAM/MRAM L2 cache. The proposed method combines dynamic cache management such as resource allocation, way-based power gating, and data migration with dynamic voltage and frequency scaling of processing cores in a temperature- and energy-aware manner. Experimental results show that the proposed runtime method with the 3-D stacked hybrid L2 cache offers up to 107.37% (55.28% on average) performance improvement and 88.47% (47.65% on average) energy efficiency improvement compared with existing thermal management methods with 3-D stacked SRAM-based L2 cache. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | POWER MANAGEMENT | - |
dc.subject | MEMORY | - |
dc.subject | DESIGN | - |
dc.subject | ENERGY | - |
dc.subject | ARCHITECTURES | - |
dc.subject | CONSTRAINTS | - |
dc.subject | PERFORMANCE | - |
dc.subject | ALLOCATION | - |
dc.subject | SYSTEMS | - |
dc.subject | CMPS | - |
dc.title | Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache | - |
dc.type | Article | - |
dc.identifier.wosid | 000350208700010 | - |
dc.identifier.scopusid | 2-s2.0-85027928850 | - |
dc.type.rims | ART | - |
dc.citation.volume | 23 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 520 | - |
dc.citation.endingpage | 533 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2014.2311798 | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.nonIdAuthor | Kang, Kyungsu | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | 3-D integration | - |
dc.subject.keywordAuthor | dynamic cache management | - |
dc.subject.keywordAuthor | dynamic voltage and frequency scaling (DVFS) | - |
dc.subject.keywordAuthor | hybrid cache | - |
dc.subject.keywordAuthor | thermal management | - |
dc.subject.keywordPlus | POWER MANAGEMENT | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | ENERGY | - |
dc.subject.keywordPlus | ARCHITECTURES | - |
dc.subject.keywordPlus | CONSTRAINTS | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | ALLOCATION | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | CMPS | - |
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