A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS

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dc.contributor.authorYoo, Taegeunko
dc.contributor.authorYeoh, Hong Changko
dc.contributor.authorJung, Yun-Hwanko
dc.contributor.authorCho, Seong-Jinko
dc.contributor.authorKim, Yong Sinko
dc.contributor.authorKang, Sung-Moko
dc.contributor.authorBaek, Kwang-Hyunko
dc.date.accessioned2015-04-07T02:43:05Z-
dc.date.available2015-04-07T02:43:05Z-
dc.date.created2014-12-29-
dc.date.created2014-12-29-
dc.date.issued2014-12-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.12, pp.2976 - 2989-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/195122-
dc.description.abstractThis paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm(2) with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz . 2((SFDR/6))/W.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectPIPELINED PHASE ACCUMULATOR-
dc.subjectINP DHBT TECHNOLOGY-
dc.subject0.18-MU-M SIGEBICMOS TECHNOLOGY-
dc.subjectSINE-WEIGHTED DAC-
dc.subjectMU-M CMOS-
dc.subjectCLOCK FREQUENCY-
dc.subjectROM-
dc.subjectPERFORMANCE-
dc.subjectDDFSS-
dc.subjectAPPROXIMATION-
dc.titleA 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS-
dc.typeArticle-
dc.identifier.wosid000345620100021-
dc.identifier.scopusid2-s2.0-84913603591-
dc.type.rimsART-
dc.citation.volume49-
dc.citation.issue12-
dc.citation.beginningpage2976-
dc.citation.endingpage2989-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/JSSC.2014.2359674-
dc.contributor.nonIdAuthorYoo, Taegeun-
dc.contributor.nonIdAuthorYeoh, Hong Chang-
dc.contributor.nonIdAuthorJung, Yun-Hwan-
dc.contributor.nonIdAuthorCho, Seong-Jin-
dc.contributor.nonIdAuthorKim, Yong Sin-
dc.contributor.nonIdAuthorBaek, Kwang-Hyun-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorDirect digital frequency synthesizer (DDFS)-
dc.subject.keywordAuthordigital-to-analog converter (DAC)-
dc.subject.keywordAuthorsegmented nonlinear DAC-
dc.subject.keywordAuthorphase accumulator-
dc.subject.keywordAuthorCMOS current mode logic-
dc.subject.keywordPlusPIPELINED PHASE ACCUMULATOR-
dc.subject.keywordPlusINP DHBT TECHNOLOGY-
dc.subject.keywordPlus0.18-MU-M SIGEBICMOS TECHNOLOGY-
dc.subject.keywordPlusSINE-WEIGHTED DAC-
dc.subject.keywordPlusMU-M CMOS-
dc.subject.keywordPlusCLOCK FREQUENCY-
dc.subject.keywordPlusROM-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusDDFSS-
dc.subject.keywordPlusAPPROXIMATION-
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