A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS

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This paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm(2) with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz . 2((SFDR/6))/W.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2014-12
Language
English
Article Type
Article
Keywords

PIPELINED PHASE ACCUMULATOR; INP DHBT TECHNOLOGY; 0.18-MU-M SIGEBICMOS TECHNOLOGY; SINE-WEIGHTED DAC; MU-M CMOS; CLOCK FREQUENCY; ROM; PERFORMANCE; DDFSS; APPROXIMATION

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.12, pp.2976 - 2989

ISSN
0018-9200
DOI
10.1109/JSSC.2014.2359674
URI
http://hdl.handle.net/10203/195122
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