Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

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dc.contributor.authorKim, Dae Hyunko
dc.contributor.authorAthikulwongse, Kritko
dc.contributor.authorHealy, Michael B.ko
dc.contributor.authorHossain, Mohammad M.ko
dc.contributor.authorJung, Moongonko
dc.contributor.authorKhorosh, Ilyako
dc.contributor.authorKumar, Gokulko
dc.contributor.authorLee, Young-Joonko
dc.contributor.authorLewis, Dean L.ko
dc.contributor.authorLin, Tzu-Weiko
dc.contributor.authorLiu, Changko
dc.contributor.authorPanth, Shreepadko
dc.contributor.authorPathak, Mohitko
dc.contributor.authorRen, Minzhenko
dc.contributor.authorShen, Guanhaoko
dc.contributor.authorSong, Taigonko
dc.contributor.authorWoo, DHko
dc.contributor.authorZhao, Xinko
dc.contributor.authorKim, Joung-Hoko
dc.contributor.authorChoi, Hoko
dc.contributor.authorLoh, Gabriel H.ko
dc.contributor.authorLee, Hsien-Hsin S.ko
dc.contributor.authorLim, Sung Kyuko
dc.date.accessioned2015-03-27T08:36:22Z-
dc.date.available2015-03-27T08:36:22Z-
dc.date.created2014-01-06-
dc.date.created2014-01-06-
dc.date.issued2015-01-
dc.identifier.citationIEEE TRANSACTIONS ON COMPUTERS, v.64, no.1, pp.112 - 125-
dc.identifier.issn0018-9340-
dc.identifier.urihttp://hdl.handle.net/10203/194558-
dc.description.abstractThis paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 mu m-diameter, 6 mu m-height through-silicon vias (TSVs) and mu m-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.titleDesign and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)-
dc.typeArticle-
dc.identifier.wosid000346572100011-
dc.identifier.scopusid2-s2.0-84919496667-
dc.type.rimsART-
dc.citation.volume64-
dc.citation.issue1-
dc.citation.beginningpage112-
dc.citation.endingpage125-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPUTERS-
dc.identifier.doi10.1109/TC.2013.192-
dc.contributor.localauthorKim, Joung-Ho-
dc.contributor.nonIdAuthorKim, Dae Hyun-
dc.contributor.nonIdAuthorAthikulwongse, Krit-
dc.contributor.nonIdAuthorHealy, Michael B.-
dc.contributor.nonIdAuthorHossain, Mohammad M.-
dc.contributor.nonIdAuthorJung, Moongon-
dc.contributor.nonIdAuthorKhorosh, Ilya-
dc.contributor.nonIdAuthorKumar, Gokul-
dc.contributor.nonIdAuthorLee, Young-Joon-
dc.contributor.nonIdAuthorLewis, Dean L.-
dc.contributor.nonIdAuthorLin, Tzu-Wei-
dc.contributor.nonIdAuthorLiu, Chang-
dc.contributor.nonIdAuthorPanth, Shreepad-
dc.contributor.nonIdAuthorPathak, Mohit-
dc.contributor.nonIdAuthorRen, Minzhen-
dc.contributor.nonIdAuthorShen, Guanhao-
dc.contributor.nonIdAuthorSong, Taigon-
dc.contributor.nonIdAuthorWoo, DH-
dc.contributor.nonIdAuthorZhao, Xin-
dc.contributor.nonIdAuthorChoi, Ho-
dc.contributor.nonIdAuthorLoh, Gabriel H.-
dc.contributor.nonIdAuthorLee, Hsien-Hsin S.-
dc.contributor.nonIdAuthorLim, Sung Kyu-
dc.type.journalArticleArticle-
dc.subject.keywordAuthor3D Multiprocessor-memory stacked systems-
dc.subject.keywordAuthor3D integrated circuits-
dc.subject.keywordAuthorComputer-aided design-
dc.subject.keywordAuthorRTL implementation and simulation-
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