Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

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This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 mu m-diameter, 6 mu m-height through-silicon vias (TSVs) and mu m-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.
Publisher
IEEE COMPUTER SOC
Issue Date
2015-01
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPUTERS, v.64, no.1, pp.112 - 125

ISSN
0018-9340
DOI
10.1109/TC.2013.192
URI
http://hdl.handle.net/10203/194558
Appears in Collection
EE-Journal Papers(저널논문)
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