Quasi-Primitive Block-wise Concatenated BCH Codes for NAND Flash Memories
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Daesung | ko |
| dc.contributor.author | Ha, Jeongseok | ko |
| dc.date.accessioned | 2015-03-27T06:58:57Z | - |
| dc.date.available | 2015-03-27T06:58:57Z | - |
| dc.date.created | 2014-11-25 | - |
| dc.date.created | 2014-11-25 | - |
| dc.date.created | 2014-11-25 | - |
| dc.date.issued | 2014-11-05 | - |
| dc.identifier.citation | IEEE Information Theory Workshop 2014 (ITW2014), pp.611 - 615 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/194406 | - |
| dc.description.abstract | In this work, we consider high-rate error-control systems based on block-wise concatenated Bose-Chaudhuri-Hocquenghem (BC-BCH) codes with iterative hard-decision decoding (IHDD) for storage devices using multi-level per cell (MLC) NAND flash memories. In particular, we propose a novel design rule of BC-BCH codes which consists of quasi-primitive BCH codes and block-wise concatenation of the constituent codes. Comprehensive performance comparisons are carried out among error-control systems with various coding schemes such as BCBCH codes and LDPC codes. | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | Quasi-Primitive Block-wise Concatenated BCH Codes for NAND Flash Memories | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000411449000124 | - |
| dc.identifier.scopusid | 2-s2.0-84929300503 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 611 | - |
| dc.citation.endingpage | 615 | - |
| dc.citation.publicationname | IEEE Information Theory Workshop 2014 (ITW2014) | - |
| dc.identifier.conferencecountry | AT | - |
| dc.identifier.conferencelocation | Hobart Function and Conference Centre, Tasmania | - |
| dc.embargo.liftdate | 9999-12-31 | - |
| dc.embargo.terms | 9999-12-31 | - |
| dc.contributor.localauthor | Ha, Jeongseok | - |
| dc.contributor.nonIdAuthor | Kim, Daesung | - |
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