DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Kwang-Seok | ko |
dc.contributor.author | Kim, Young-Hwa | ko |
dc.contributor.author | Yu, Won-Sik | ko |
dc.contributor.author | Cho, Seong-Hwan | ko |
dc.date.accessioned | 2014-11-28T02:21:31Z | - |
dc.date.available | 2014-11-28T02:21:31Z | - |
dc.date.created | 2012-10-30 | - |
dc.date.created | 2012-10-30 | - |
dc.date.issued | 2013-04 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, pp.1009 - 1017 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/191228 | - |
dc.description.abstract | In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate, and programmable gain for a wide input range. Using the proposed pulse-train time amplifier, a 7-bit two-step TDC is implemented. The proposed TDC employs repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. The prototype chip fabricated in 65 nm CMOS process achieves 3.75 ps of time resolution at 200 MS/s while consuming 3.6 mW and occupying 0.02 mm(2) area. Compared to previously reported TDCs, the proposed TDC achieves the fastest conversion rate and the best FoM without any calibration. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DELAY-LINE | - |
dc.subject | TDC | - |
dc.title | A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier | - |
dc.type | Article | - |
dc.identifier.wosid | 000316810500013 | - |
dc.identifier.scopusid | 2-s2.0-84875745342 | - |
dc.type.rims | ART | - |
dc.citation.volume | 48 | - |
dc.citation.beginningpage | 1009 | - |
dc.citation.endingpage | 1017 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2013.2237996 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.contributor.nonIdAuthor | Kim, Young-Hwa | - |
dc.contributor.nonIdAuthor | Yu, Won-Sik | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Time-to-digital converter (TDC) | - |
dc.subject.keywordAuthor | time amplifier | - |
dc.subject.keywordAuthor | two-step architecture | - |
dc.subject.keywordAuthor | PLL and all-digital PLL (ADPLL) | - |
dc.subject.keywordAuthor | time-domain ADC | - |
dc.subject.keywordPlus | DELAY-LINE | - |
dc.subject.keywordPlus | TDC | - |
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