A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier

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dc.contributor.authorKim, Kwang-Seokko
dc.contributor.authorKim, Young-Hwako
dc.contributor.authorYu, Won-Sikko
dc.contributor.authorCho, Seong-Hwanko
dc.date.accessioned2014-11-28T02:21:31Z-
dc.date.available2014-11-28T02:21:31Z-
dc.date.created2012-10-30-
dc.date.created2012-10-30-
dc.date.issued2013-04-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, pp.1009 - 1017-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/191228-
dc.description.abstractIn this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate, and programmable gain for a wide input range. Using the proposed pulse-train time amplifier, a 7-bit two-step TDC is implemented. The proposed TDC employs repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. The prototype chip fabricated in 65 nm CMOS process achieves 3.75 ps of time resolution at 200 MS/s while consuming 3.6 mW and occupying 0.02 mm(2) area. Compared to previously reported TDCs, the proposed TDC achieves the fastest conversion rate and the best FoM without any calibration.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDELAY-LINE-
dc.subjectTDC-
dc.titleA 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier-
dc.typeArticle-
dc.identifier.wosid000316810500013-
dc.identifier.scopusid2-s2.0-84875745342-
dc.type.rimsART-
dc.citation.volume48-
dc.citation.beginningpage1009-
dc.citation.endingpage1017-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/JSSC.2013.2237996-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorCho, Seong-Hwan-
dc.contributor.nonIdAuthorKim, Young-Hwa-
dc.contributor.nonIdAuthorYu, Won-Sik-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordAuthorTime-to-digital converter (TDC)-
dc.subject.keywordAuthortime amplifier-
dc.subject.keywordAuthortwo-step architecture-
dc.subject.keywordAuthorPLL and all-digital PLL (ADPLL)-
dc.subject.keywordAuthortime-domain ADC-
dc.subject.keywordPlusDELAY-LINE-
dc.subject.keywordPlusTDC-
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